Ever wonder the effects of shared anti-pads on differential signals?

Posted Mar 23, 2011, by Zhen Mu

Print this Post

Tags: ZM_shared_anti_pad

0 Comments

By Zhen Mu & Jian X. Zheng 

Vias are the structures that exist on almost every net in high speed digital PCB designs. Because of its 3-dimensional features, a via introduces reflections to signals traveling through it. Designers and Signal Integrity (SI) engineers have been trying hard to design vias that present minimum degradation impact on signals. This becomes an even more important task in SERDES designs where the data rates are approaching 25Gbps.

One design method to reduce via discontinuity effect is to use a shared anti-pad for differential vias in connector pin fields, as Figure 1 illustrates.

Figure 1 Using shared anti-pad in connector pin fields
Figure 1 Using shared anti-pads in connector pin fields

Studies show that the benefit using shared anti-pads in this way is reduced capacitance load to planes. What has not been fully discussed is whether the benefit holds when differential traces are connected to the vias that use shared anti-pads; in other words, what would the signal quality be when differential signals go through a pair of differential vias with shared anti-pads? Figure 2 shows the configuration of such cases.

Microsoft PowerPoint - Zhens images [Compatibility Mode]

Figure 2 Using shared anti-pad on differential signal path

One thing to pay attention to is the area under the feeding traces that connect to the differential vias. We can compare this area in the shared anti-pad configuration with the one using separate anti-pads shown in Figure 3. The shared anti-pad takes away part of via coupling to planes, which reduces the capacitance between via barrow and planes; however, it also takes away the reference plane, or the return path, of the feeding traces when they are approaching the connection points to vias. Of course, the effect can be less significant in the case of tightly coupled differential, but it will always be there.

Figure 3 Using separate anti-pad on differential signal path
Figure 3 Using separate anti-pad on differential signal path

Next, let’s  take a look at the S-parameter models extracted from the two structures in Figure 2 and 3. Both of them have the same geometry parameters, except one uses separate anti-pads, and the other shares anti-pads in a shape close to “Oblong”. The 12 layer stackup is shown in Figure 4. All the inner layers are planes for the purpose of study.

Figure 4 Stackup of a 12-layer design
Figure 4 Stackup of a 12-layer design

Figure 5 provides comparison of insertion loss from the two structures. We can see that both S-parameter models behave very similarly before the first resonance point; but the shared anti-pads increase the loss a little in the frequency range of 2GHz to 8GHz, because of the reference plane reduction, while they help shift the resonant peak further to higher frequencies (from 18GHz to 18.5GHz) due to the reduced capacitance load.

Figure 5 Comparing insertion loss (12 layer design) -- Purple: shared anti-pads; Blue: separated round anti-pads
Figure 5 Comparing insertion loss (12 layer design) — Purple: shared anti-pads; Blue: separated round anti-pads

Another test case with fewer layers reveals similar results. Figure 6 shows comparisons of S-parameters of a 6 layer design. Shared anti-pads do not show their benefits until via-to-plane capacitance starts being effective; before that happens, using separate anti-pads actually provides better signal quality.

Figure 6 Comparing insertion loss (6 layer design), Purple and Green: shared anti-pads, Blue and Yellow-: separated round anti-pads
Figure 6 Comparing insertion loss (6 layer design), Purple and Green: shared anti-pads, Blue and Yellow-: separated round anti-pads

 

In summary, the study shows that using shared anti-pads for routed differential signal paths is probably more meaningful to physical layout than to improving signal quality. The effect of shared anti-pads is frequency dependent, and the gain from reduced capacitive loading is achieved by sacrificing certain portions of signal return path. Designers should be aware of such trade-off when applying the technique. 

Reference

[1] Ravi Kollipara and Ben Chia, Modeling, verification of backplane press-fit vias, EETimes India, Oct.2004

[2] B. Wu and L. Tsang, FULL-WAVE MODELING OF MULTIPLE VIAS USING DIFFERENTIAL SIGNALING AND SHARED ANTIPAD IN MULTILAYERED HIGH SPEED VERTICAL INTER-CONNECTS, Progress In Electromagnetics Research, PIER 97, 129-139, 2009

Preparing Recommendations

About Zhen Mu

image Visit AskJian

More Posts by Zhen Mu

More Blog Posts

Preparing Recommendations

Comments

No one has commented yet on this post. Be the first to comment below.

Add Your Comment

Please complete the following information to comment or sign in.

(Your email will not be published)