PCB design trends show increasing complexity

PCB design trends show increasing complexity

The Mentor Graphics annual Technology Leadership Awards competition provides a snapshot of PCB design trends across all electronics industries. I’ve included a table below based on TLA entry averages.

As expected, there’s a general theme of increased design density over the years. This can be seen in the reduction of trace widths/clearances and average pins/in2. The board size and layer count have stayed relatively the same, except for consumer and industrial applications – but everyone’s having to put a ton more functionality in the same form factor. For layer stack-ups there used to be a clear distinction between power/ground and signal layers. Now, to support an increase in voltage and current requirements within a fixed layer count, planes are often are often combined with other planes and signals on a layer. This creates a host of challenges including current delivery, voltage drop, impedance control, current return paths, and noise management.

The transition from many mid-sized components to a few actives with tons of supporting passives is driven by continuing system integration on chip. There is a corresponding increase in nets and connections (more functionality per chip), and a decrease in average leads/part (high percentage of 2-pin resistors and capacitors).

Telecom/networking cards continue to set the mark for size (board area, layers) and number of components/nets/connections/vias. Consumer electronics are on the other end of the board size scale, while managing the highest design densities. The percentage of high-speed-constrained nets is up across all industries, but computer designs maintain the lead.

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Design 15 years ago

• Clocks were around 66MHz, and signals had nanosecond rise times – quite pedestrian by today’s picosecond standards.
• Placement was dual-sided, with SMD emerging as the standard. Vias were mostly through-hole.

Design 10 years ago

• Processors were around 750MHz, clocks at 100MHz, and rise times dipped under a nanosecond.
• BGAs were starting to gain popularity, but only had 100-200 pins.
• Microvias were emerging as a solution to the design density challenge.
• ‘Small’ cell phone boards were 5” tall.
• Many nets had basic impedance control/constraints as design for performance became more common.

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