The cure for sick waveforms

The cure for sick waveforms

Found a signal integrity problem in the lab?  How do you go about fixing it?  Well, if it’s a SERDES bus, you can’t do any kind of re-work because it will most likely kill the signal even more.  Maybe you can play with some driver strength or pre-emphasis settings.  Or is it a slower, parallel bus?  Maybe you can re-work in some necessary termination.  This is where post-layout SI simulation is useful.  In simulation, you can mimic the problematic situation, and try to figure out a solution, without even touching a soldering iron.  And what’s more, you can simulate all the nets on the board to make sure they don’t have similar problems.

In fact, you wouldn’t be in such a situation if you did a full-board SI verification before sending it to the fab house.  Better yet, if you did some pre-layout simulation to identify the necessary constraints on the critical busses, there may not have even been a problem to find in post-layout simulation.  In every step of the design phase, changes become orders of magntiude more costly and time-consuming.  That’s where doing the bulk of your signal integrity (and power integrity) work towards the beginning of the design cycle really pays off.
You can read more about it here:
http://electronicdesign.com/article/eda/whats-difference-prelayout-postlayout-pcb-simulation-73640

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