TLA 2011 Is Just Around The Corner!

TLA 2011 Is Just Around The Corner!

The 2011 Technology Leadership Awards competition starts next week. This competition showcases the best PCB designs (and designers) from around the world representing all major electronics industries.The critical dates are:

• August 2: Site is open for new entries
• September 30: Deadline for entries
• November 17: Winners announced

Check out the 2010 winners and review the details of last year’s overall winner below to get an idea of the designs that get submitted.

2010 Technology Leadership Awards: Overall winner

The 2010 TLA competition featured stiff competition in all categories. In addition to winners in each industry category, an overall winner was also selected. GE Intelligent Platforms won this award with a ‘military & aerospace’ category entry.

Design team: Paul Curran, Mike Tapp, Rob Savage, John Digby

End product use: Rugged 6U VPX single board computer. This specialist family of products is aimed at high performance mil/aero applications.

Stats:

Design challenges:

• Design for…signal/power integrity, cost and manufacturability.
• Complexity: 3,500+ nets; 20,000+ connections; 11,600+ vias; 8,500+ components; total 20 BGAs placed on both sides – several quad flat packs with 0.4mm pitch also used.
• Thermal management: Processor was low power (30W), but still needed to place close to a cold wall due to operation at temperatures up to 85C. All components had to be rated for -45C to 85C for ruggedization.
• Mechanical: Mezzanine plug-in cards dictated low profile placement regions.
• Buried vias: Reduced buried via pairs to cut costs – increased routing challenge.
• High-speed signaling: Serial Rapid I/O, PCI-X, DDR3 – significant constraints with tight tolerances. Placed solid continuous ground layers on either side of over 500 diff pairs to minimize impedance discontinuities.
• Power: Managed trade-offs between power consumption and thermal management. Ensured that the PCB could deliver the required 30A current.
• Significant effort taken in placement to ensure thermal efficiency, effective power delivery, and sufficient routing channels including tuning space.
• 14 power rails – placed on two internal layers – shielded signals from power noise with ground plane on either side. Manually increased power trace widths wherever possible to increase current capacity for critical devices.
• The stack-up created for this design has been successfully used for other designs and has become the new standard.

Design tools:

• Expedition Enterprise flow
  • I/O Designer: “The major design challenge was routing the processor and connecting components. Because the number of routing channels and layers was limited it was important to reduce the number of crossover connections between the devices. I/O Designer was used extensively to manage the unravelling of these connections. By maintaining consistency between the PCB and Schematic data the team could quickly and easily with confidence perform the necessary pin-swaps to optimize the routing without compromising the FPGA internal design. “
  • CES: “Constraints for the data buss’s and clock’s high-speed and timing were entered and managed using the Constraints Editing System. Constraint templates were created for each buss and clock technology group that included the required topology and rules sets. Once defined these were then applied to all relevant nets greatly reducing the time to enter the data. “
  • XtremePCB: “Due to the aggressive project timescales the design team worked concurrently. Before the schematics were fully complete, layout started on the processor/memory section, with updates for both constraints and schematic changes being forward annotated at appropriate stages of the design. Concurrent design was taken a stage further by the use of XtremePCB. Two layout designers routed the board simultaneously with each designer taking ownership of distinct areas of the board such as DDR3, PCI-X, Ethernet etc. “
  • “The pre-layout planning coupled with the concurrent design process and XtremePCB resulted in the board being completed approximately two weeks earlier than scheduled. “

Judge’s comments:

• “One of the best designs for TH (through hole) boards with HDI density of372 pins/sq inch. Exceptional TH layout with 27% layout efficiency where TH normally gets on 6~12%.”

   

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