What's important when you want to "design for the lowest cost"?
What's important when you want to "design for the lowest cost"?
In addition to “doing everything right”, I think there are 6 other ideas that can help lower the manufacturing cost of a PCB.
1. Understanding First Pass Yield (FPY) in Mfg.- The mfg. yield of a PCB can be predicted for a particular fabricator by ‘calibrating’ that fabricator’s capability. 75% of the cost of a PCB is based on the design (20 - 25% is cost of inventory and factors not related to the PCB process) and average yield is based on how “complex” the design is. More layers, finer lines, larger size, smaller holes, total number of holes, etc all make the PCB ‘complex’ to manufacturer. So once you have a fabricators “Capability Coefficients”, you can take the PCB Complexity Index (made up of critical design features) and estimate the FPY. This can be as accurate as +/- 3-5% if the fabricator has his manufacturing process under control (not to much design can do if employees are not trained, quality procedures not observed or equipment not maintained). This FPY provides insight into how much this design will cost with this fabricator.
2. Selecting the best PCB materials to lower costs-Many are not familiar with the mfg’s of laminates in Asia, even though they are now the largest materials suppliers in the world. NanYa Plastics, Panasonic and Kingboard are No. 1, 2 & 3 in the world. Because of this they have some of the lowest priced FR-4 laminates that meet all the MIL & IPC specs for FR-4, including lead-free assembly. Newer laminators like ITEQ, ShengYi, Doosan, Chang Chan, Grace and TUC are now also in the North American market selling their laminates. Since laminate is the single largest cost of a PCB, it makes reviewing these new suppliers worth the effort.
Preparing Recommendations3. How to reduce layers in a PCB multilayer-Mentor has developed a better strategy for fanout of BGAs > 400 pins that can lead to reducing the number of signal layers in a board. If HDI-microvias are also used, then the layer reduction can be significant with these new ‘aligned-via patterns’. The layer reduction is large enough to pay for the increased price of HDI, plus some extra!
4. Design for Fab (DFF) Best Practices-Nothing beats “Best Practices” in terms of design rules, spacings and other layout techniques that minimize fabrication and assembly problems.
5. Understanding if a PCB Fabricator is Capable of building your design at high FPYs.- What if a fabricator’s FPY is low for your design? IPC has created a Benchmarking Program that test a fabricators capability, the IPC-9151 Benchmarking Panels. This is a set of PCB panels from 2 to 24 layers, created with different hole, pad, trace and spacing geometries. The artwork is free and available at http:///www.pcbquality.com . A fabricator can download the artwork and build the Benchmarked panels. There are two licensed facilities that have the extensive test equipment to evaluate these panles and produce the comprehensive report. The Program is called PCQR2, for Process Capability, Quality and Relative Reliability, because it also takes the via daisy-chains and subjects them to 500 cycles of -45C to 145C. The panels are designed to provide a 99% confidence of only a 1% error statistically in the data.
6. Since Volume is the No. 1 PCB Cost-driver, what about Asian Fabrication (China)? There are a lot of N.A.PCB prototype houses and sales organizations representing the vast number of PCB fabricators in Taiwan, Japan, Korea, Thailand, Mayasia and China. If you are confident that a fabricator in Asia is ‘capable’ of building your board, then Asia has the lowest prices. Asia many times also wants very high volume, but there is a growing number of Asian fabricators that specialize on lower volumes and even the techniques of mixing a number of different PNs (proving they are the same thickness and layers) on the same production panel. This allows for a larger Order Quantity.
More Blog Posts
Preparing RecommendationsRecent Posts
- Fabrication and Assembly Analysis?
- Advanced tools mitigates risks with Embedded Passives (EP’s)
- Embedded passives never boomed –but saves high performance designs
- Gerber to ODB++ - Have You Made the Move?
- Shorter stubs are getting longer
- Stupid vias... {grumble grumble}
- Via modeling - what do I really need?
- Using Virtual Prototyping versus Physical Prototyping
- Best-in-class companies use design concurrency
- Don't miss out - Technology Leadership Awards contest
Comments
No one has commented yet on this post. Be the first to comment below.
Add Your Comment
Please complete the following information to comment or sign in.