Posts tagged with 'DDR3'
In the past I have blogged about crossing splits in reference planes. This is probably the most glaringly obvious of reference plane changes, and will of course result in radiation from the signal.
But another type of reference plane change which is more common, and usually much less avoidable, is when a signal transitions layers through a via. In such a case, the reference planes will change and … Read More
Yeah, I can totally see Homer Simpson designing his SERDES bus and getting frustrated by all the additional insertion loss caused by his vias, and muttering to himself, “Stupid vias…” and grumbling. And then going into the lab, looking at his failing eye diagram, and shouting “D’oh!”. Okay, well Homer Simpson probably won’t be designing any SERDES busses anytime … Read More
DDR3, PCI Express, DDR2, via
Whether you are trying to correlate simulated waveforms to measured waveforms for a DDR3 signal, or board timing numbers for a simple SDRAM bus, or measured Z-parameters when looking at a PDN impedance, or even just a simple trace impedance measurement on the TDR, it all begins with the proper stackup. I explore some of the commonly overlooked nuances of stackup modeling in my recent article in InCompliance … Read More
Last week I held a web seminar on the HyperLynx DDRx wizard. This was an overview on DDR3 technology and also included a demonstration of the HyperLynx DDRx wizard. Hopefully you had a chance to view it but if not, you can view the recording here:
http://www.mentor.com/products/pcb-system-design/multimedia/ddrx-design-webinar
This week, my friends in customer support have put together a comprehensive … Read More