PCB Systems Design Blog

Posts tagged with 'HyperLynx'

Turn off your phone!

Posted May 3, 2012, by Patrick Carrier

Everybody knows you are supposed to turn off your phone and other electronic devices when you are on a plane.  You can leave it on during the flight, but it has to be off for takeoff and landing.  I like to remind people in case they “forget”.  I tend not to make a big deal during takeoff, but landing has me a little more on edge. The problem is coupled noise.  Sure, most modern planes … Read More

Tags: crosstalk, HyperLynx, coupled noise, noise coupling

Is it SSN or is it Crosstalk?

Posted May 2, 2012, by Patrick Carrier

In the lab, both simultaneous switching noise (SSN) and crosstalk look the same.  They appear as unwanted pulses of energy that line up with the (aggressor) signal edges.  However, the mode of energy coupling is much different between SSN and crosstalk.  In the case of crosstalk, they are lining up with the edges because the signal edges are coupling energy onto the victim signal through electric (and … Read More

Tags: crosstalk v SSN, HyperLynx, crosstalk, simultaneous switching noise, SSN

Crosstalk is everywhere

Posted May 1, 2012, by Patrick Carrier

Crosstalk is everywhere.  Really, in a more general sense, noise coupling is everywhere.  Usually the method of noise coupling is traditional “crosstalk” – the unwanted transfer of noise from one place to another through coupled electric fields.  This most often occurs on PCB designs with dense routing, and on wide parallel busses.  Even on newer SERDES busses, however, it is still … Read More

Tags: crosstalk, HyperLynx, connector crosstalk, via coupling, noise coupling, SSN

The cure for sick waveforms

Posted Apr 3, 2012, by Patrick Carrier

Found a signal integrity problem in the lab?  How do you go about fixing it?  Well, if it’s a SERDES bus, you can’t do any kind of re-work because it will most likely kill the signal even more.  Maybe you can play with some driver strength or pre-emphasis settings.  Or is it a slower, parallel bus?  Maybe you can re-work in some necessary termination.  This is where post-layout SI simulation … Read More

Tags: post-layout, Pre-Layout, HyperLynx, Signal Integrity

Running at 6GHz with your eyes closed can be scary

Posted Mar 31, 2012, by Patrick Carrier

Running at 6GHz is actually kind of scary regardless, but especially so with your eyes closed.  And I mean that more figuratively than literally.  Obviously, if your eye diagrams are closed on your serial links in your design there is cause for fear, but the fear of the unknown can be even greater, especially if you are running at multi-GHz speeds.  That is where a complement of pre-layout and post-layout … Read More

Tags: HyperLynx, post-layout, 6GHz, SATA, Signal Integrity, Pre-Layout, SAS

It's never too late

Posted Mar 29, 2012, by Patrick Carrier

It’s never too late to fix a design problem.  Well, maybe if the product is shipping, that might be classified as “too late”.  But during the design phase, whether you’ve laid out your board or not, it’s a good time to make sure there are no design issues.  When it comes to signal integrity, that means performing pre-layout or post-layout simulations.  I think most experts … Read More

Tags: post-layout, Pre-Layout, HyperLynx, Signal Integrity

The Parallel Pain

Posted Mar 7, 2012, by Patrick Carrier

Parallel busses are a pain to implement.  They really are.  Sure, they are slower than blazing-fast SERDES busses, but they introduce a lot more problems.  SERDES busses introduce a new set of problems because they are so fast, but they are also differential and serial, which eliminates a bunch of problems.  Parallel busses are single-ended, so they tend to draw a lot more power.  So that means you … Read More

Tags: DDR3, HyperLynx, DDR2, slew rate derating, write leveling, parallel, parallel bus

Put the Pieces in Place for SERDES Success

Posted Mar 6, 2012, by Patrick Carrier

Interconnect loss modeling?  Check.  Signal conditioning modeling?  Check.  Ability to simulate multiple S-parameter models for things like connectors and packages and vias correctly in the time domain?  Oooh…. that’s a tough one.  Check! Ability to include all sources of deterministic and random jitter, worst-case bit patterns, and worst-case crosstalk in the analysis?  Wow!  Check. 3D … Read More

Tags: SERDES, pre-emphasis, BER, channel analysis, 3D via, HyperLynx, interconnect loss, crosstalk, equalization

Know your limits

Posted Mar 5, 2012, by Patrick Carrier

“A man’s got to know his limitations” … true, and so does a digital bus.  Clint Eastwood’s quote to conclude the movie Magnum Force in 1973 also applies to digital busses.  Of course, back then, signal edge rates were slow enough that most people didn’t have to care too much about signal integrity.  And now, in sharp contrast, we’ve progressed to the point where … Read More

Tags: bit error rate, DDR3, BER, SERDES, equalization, HyperLynx

Shorter stubs are getting longer

Posted Nov 4, 2011, by Patrick Carrier

…It all depends on how fast you are trying to go.  That’s really the name of the game with anything signal integrity.  The faster we go, the more “new” problems we face.  Even if a stub were 50 mils long, if your edge rate is fast enough, such as the edge rates used in many SERDES busses today, it could be enough to fatally degrade your received signal. At the beginning of my … Read More

Tags: 3D via, HyperLynx, 3D field solver, vias, stub, via