Found a signal integrity problem in the lab? How do you go about fixing it? Well, if it’s a SERDES bus, you can’t do any kind of re-work because it will most likely kill the signal even more. Maybe you can play with some driver strength or pre-emphasis settings. Or is it a slower, parallel bus? Maybe you can re-work in some necessary termination. This is where post-layout SI simulation … Read More
Tags: post-layout, Pre-Layout, HyperLynx, Signal Integrity
Running at 6GHz is actually kind of scary regardless, but especially so with your eyes closed. And I mean that more figuratively than literally. Obviously, if your eye diagrams are closed on your serial links in your design there is cause for fear, but the fear of the unknown can be even greater, especially if you are running at multi-GHz speeds. That is where a complement of pre-layout and post-layout … Read More
Tags: HyperLynx, post-layout, 6GHz, SATA, Signal Integrity, Pre-Layout, SAS
It’s never too late to fix a design problem. Well, maybe if the product is shipping, that might be classified as “too late”. But during the design phase, whether you’ve laid out your board or not, it’s a good time to make sure there are no design issues. When it comes to signal integrity, that means performing pre-layout or post-layout simulations. I think most experts … Read More
Tags: post-layout, Pre-Layout, HyperLynx, Signal Integrity
I’ve been on a bit of a blogging hiatus, but hopefully I’m returning to a more regularly scheduled program. Consider it like the Olympics that has interrupted your regular TV programming for the last 2 weeks to show you people who have committed their lives to their passion. I enjoy it - some of those people do amazing feats often risking life and limb to be the best in the world at what they do.
The … Read More
Tags: HyperLynx, Olympic, Constraints, Pre-Layout
