Posted Mar 6, 2012, by Patrick Carrier
Interconnect loss modeling? Check.
Signal conditioning modeling? Check.
Ability to simulate multiple S-parameter models for things like connectors and packages and vias correctly in the time domain? Oooh…. that’s a tough one. Check!
Ability to include all sources of deterministic and random jitter, worst-case bit patterns, and worst-case crosstalk in the analysis? Wow! Check.
3D … Read More
Tags:
SERDES,
pre-emphasis,
BER,
channel analysis,
3D via,
HyperLynx,
interconnect loss,
crosstalk,
equalization
Posted Mar 5, 2012, by Patrick Carrier
“A man’s got to know his limitations” … true, and so does a digital bus. Clint Eastwood’s quote to conclude the movie Magnum Force in 1973 also applies to digital busses. Of course, back then, signal edge rates were slow enough that most people didn’t have to care too much about signal integrity. And now, in sharp contrast, we’ve progressed to the point where … Read More
Tags:
bit error rate,
DDR3,
BER,
SERDES,
equalization,
HyperLynx
Posted Nov 2, 2011, by Patrick Carrier
The whole via simulation issue is admittedly complicated, and I think really boils down to whether the vias are single-ended or differential, and at what speeds you are running.
When the vias are differential, the return current is basically self-contained around the vias since they have equal but opposite signals on them. Because of this, the built-in analytical model in HyperLynx models differential … Read More
Tags:
vias,
3D field solver,
HyperLynx,
3D EM,
SERDES,
via,
IE3D,
PDN
Posted Jan 14, 2011, by Patrick Carrier
In the digital design world, we have typically only seen S-parameters used to model packages. They are a popular output of 3D field solvers like IE3D. But more and more, especially in SERDES design, we are seeing S-parameters being used for a variety of parts. One of the reasons for their growing popularity is their fater simulation time, especially when advanced simulation techniques are used, as … Read More
Tags:
HyperLynx,
S-parameter,
SERDES
Posted Jan 13, 2011, by Patrick Carrier
You may have heard lately about IBIS-AMI models, which are being used more often for SERDES simulation. IBIS-AMI stands for I/O Buffer Information Specification Algorithmic Modeling Interface. These models are an addendum to the existing IBIS spec that contain executable models.
Actually the models contain 3 parts: an analog buffer model, a parameter file, and the actual executable model. The executable … Read More
Tags:
SPICE,
Fasteye,
HyperLynx,
SERDES,
IBIS,
IBIS-AMI
Posted Jan 12, 2011, by Patrick Carrier
Anyone who has ever had to simulate a SERDES interface knows how long it take to run a couple hundred bits through a SPICE model. Hours. Sometimes you have to kick it off overnight. And if you want to do some solution space exploration, probably one of the main purposes for running your simulation, it could take you a whole week of sims. I mean, you could take the time that your sim is running to … Read More
Tags:
SERDES,
SPICE,
Fasteye
Posted Jan 14, 2010, by Steve McKinney
If you do any kind of multi-gigabit SerDes design, you’ve probably come across the acronym, AMI - Algorithmic Modeling Interface. AMI is essential a fast behavioral model of multi-gigabit transmitters and receivers. Standard IBIS models are good for regular switching edges up to some surprisingly fast speeds, but when you start adding in things like pre-emphasis, and equalization on those edge, … Read More
Tags:
Multi-Gigabit,
Models,
SERDES,
ATM,
Xilinx,
Eye Diagram,
AMI,
IBIS 5.0,
SPICE,
V5,
Modeling,
HyperLynx,
Virtex 5,
Webinar,
IBIS
Posted Jan 6, 2010, by Mark Forbes
DesignCon is coming up in less than a month, February 1-4 in Santa Clara, CA (find your way to San Jose and turn left). This is a great show, and we at Mentor have put together some great sessions for you; and we have more than just technical content, we have some fun plans as well.
One of those fun things is a panel called “Science Fiction: Is It Really Fiction” Tuesday, February 2nd from 3:45 … Read More
Tags:
High Speed,
IBIS,
DesignCon,
SPICE,
SERDES,
SiP
Posted Sep 16, 2009, by Ian Dodd
Today most of us take mass-production and cheap rapid transport for granted.
In Europe at the start of the 17th century none of this existed. Goods and raw materials were produced literally as a cottage industry.
In particular Iron was produced in small pans filled with iron ore, charcoal and limestone. Batch size was limited by the inability of the charcoal to resist crushing under the weight of … Read More
Tags:
High Speed Serial Channel,
Linear Channel Analysis,
Fasteye,
SERDES,
Multi-Gbps,
Multi-GHz
