You may have heard lately about IBIS-AMI models, which are being used more often for SERDES simulation. IBIS-AMI stands for I/O Buffer Information Specification Algorithmic Modeling Interface. These models are an addendum to the existing IBIS spec that contain executable models.
Actually the models contain 3 parts: an analog buffer model, a parameter file, and the actual executable model. The executable … Read More
Anyone who has ever had to simulate a SERDES interface knows how long it take to run a couple hundred bits through a SPICE model. Hours. Sometimes you have to kick it off overnight. And if you want to do some solution space exploration, probably one of the main purposes for running your simulation, it could take you a whole week of sims. I mean, you could take the time that your sim is running to … Read More
If you do any kind of multi-gigabit SerDes design, you’ve probably come across the acronym, AMI - Algorithmic Modeling Interface. AMI is essential a fast behavioral model of multi-gigabit transmitters and receivers. Standard IBIS models are good for regular switching edges up to some surprisingly fast speeds, but when you start adding in things like pre-emphasis, and equalization on those edge, … Read More
Tags: Multi-Gigabit, Models, SERDES, ATM, Xilinx, Eye Diagram, AMI, IBIS 5.0, SPICE, V5, Modeling, HyperLynx, Virtex 5, Webinar, IBIS
DesignCon is coming up in less than a month, February 1-4 in Santa Clara, CA (find your way to San Jose and turn left). This is a great show, and we at Mentor have put together some great sessions for you; and we have more than just technical content, we have some fun plans as well.
One of those fun things is a panel called “Science Fiction: Is It Really Fiction” Tuesday, February 2nd from 3:45 … Read More
