Posts tagged with 'via'
…It all depends on how fast you are trying to go. That’s really the name of the game with anything signal integrity. The faster we go, the more “new” problems we face. Even if a stub were 50 mils long, if your edge rate is fast enough, such as the edge rates used in many SERDES busses today, it could be enough to fatally degrade your received signal.
At the beginning of my … Read More
Yeah, I can totally see Homer Simpson designing his SERDES bus and getting frustrated by all the additional insertion loss caused by his vias, and muttering to himself, “Stupid vias…” and grumbling. And then going into the lab, looking at his failing eye diagram, and shouting “D’oh!”. Okay, well Homer Simpson probably won’t be designing any SERDES busses anytime … Read More
DDR3, PCI Express, DDR2, via
The whole via simulation issue is admittedly complicated, and I think really boils down to whether the vias are single-ended or differential, and at what speeds you are running.
When the vias are differential, the return current is basically self-contained around the vias since they have equal but opposite signals on them. Because of this, the built-in analytical model in HyperLynx models differential … Read More