I/O Designer is the foundation for an effective FPGA/PCB co-design process. I/O Designer supports the latest devices offered by the FPGA vendors and can quickly convert an FPGA design into a PCB schematic, ready for layout.
In addition, I/O Designer provides correct-by-construction FPGA I/O assignment, allowing pin swapping and layout-based I/O optimization within the PCB process.
Enterprise-level FPGA-on-Board Optimization Strategies
On-demand Web Seminar This session will showcase how pin optimization technology streamlined into a component management and design flow can realize schedule and cost benefits throughout the enterprise.
An Integrated Design Flow for FPGA/PCB Co-Design
On-demand Web Seminar While FPGA pin assignment closure is seen as a painful and time consuming process by many, adoption of the right methodology can not only shorten project schedule but also differentiate your product. This...
Features and Benefits
- Provides bi-directional integration, data management and the ability to perform concurrent design of your FPGA and PCB
- Focused on optimizing system performance, designer productivity and reducing product manufacturing costs
- Eliminates the barriers between FPGA and PCB flows and design organizations
- Reduces PCB Manufacturing costs by eliminating PCB signal layers
- Makes achieving high-speed constraints possible
- Reduces the total product design cycle time by changing a serial process into a concurrent process
- Eliminates PCB re-spins due to bad FPGA symbols on the PCB
- Eliminates the costs associated with creating and maintaining the FPGA symbol(s) for the PCB schematic
I/O Designer offers a unique process for moving through the design flow, from the top level HDL description to the PCB level symbol, as well as to the physical pin information necessary for the FPGA place and route tools.
I/O Designer offers a central solution for the digital design engineer performing the HDL design and the physical implementation of the FPGA, as well as for the board designer using the device symbol.
Optimization and version control
Design process optimization and version control
I/O Designer does not only automate the schematic connectivity required for PCB layout and verification, but also document which signal connections are made to which device pins and indicate how these pins map to the original board-level bus structures. With I/O Designer and a close collaboration between the parallel paths of FPGA and PCB design, weeks and months can be trimmed from FPGA design and implementation schedule along with significant overall cost savings in the long term. I/O Designer has built-in data management capabilities that enables the designers to jointly work on the integration of an FPGA on the board and to keep track of every change made by any one of them even if they are located on disperse locations.
Bridge FPGA and PCB
Consistency bridge between FPGA and PCB environments
I/O Designer manages the consistency between the FPGA and PCB flows by acting as a data management tool, monitoring each flow and managing any changes that occur. Pin swaps carried out on the PCB are picked up by I/O Designer and the necessary files updated. I/O Designer then generates FPGA place and route constraints, based on the HDL design and pin I/O assignment process, and creates the necessary symbols, schematics and hierarchical associations based on the “postroute" pin data.
Symbol Creation in Mentor Graphics native schematic formats
I/O Designer supports most industry symbol standards by offering a customizable library of pin and symbol shapes. It also offers advanced features for the importing and exporting of symbols and schematics.
Import and Export native symbols and schematics
- Design Capture
- Design Architect
- Board Architect
In addition to that, import schematic symbols:
I/O Designer also provides an easy to use interface that contains a schematic symbol window that allows signals or pins to be dragged and dropped and a graphical display of footprints to map signals to pins. This interface allows for on-the-fly updates that are immediately reflected within the Mentor PCB tools and then written out to the FPGA tools.
- FPGA pin assignment with place & route
- Intelligent I/O design
- All pin information available during I/O design
- PCB layout optimization
- Pinswap back-annotation
- Windows7 x86/x64
- Windows Server 2008 x86/x64
- Windows Vista x86/x64
- Windows XP x86
- Linux RHEL 4 x86 and Linux RHEL 5 x*^-64
- Linux SLES 10 x86-64
- Solaris 10 UltraSPARC
- Time based
- Floating: Windows 2000, XP, Solaris, HP-UX, Linux
- FlexLM protected