CES Fundamentals Tips & Tricks Workshop
There are currently no dates scheduled for this event.
Overview
The CES Fundamentals, Tips & Tricks workshop was developed to provide a practical guideline through the constrained process of your design. The fundamental part explains the usage of CES and principles in the Expedition Enterprise Flow. It also provides basic knowledge on the tasks an electrical engineer needs to meet and how this influences the PCB designers demands. You will also learn in a task oriented way, how design specifications are converted into constraints. The workshop will conclude with some practical examples and additional tips and tricks, using a DDR2 example where most of the learned methodologies are passed as a final review.
Practical lab exercises help reinforce what is discussed during the lectures and provide you with the necessary tool use to make your next design more efficiently constrained.
CES Fundamentals
- Why
- CES in the flow
- Physical versus electrical
- Physical Fields Reviewed
- Basic
- Organizing the Design
- Physical Layout Constraints (Layouter)
- Stackup
- Net clases
- Clearances
- Controlling the G.U.I. Electrical Fields Reviewed
- Constraints reviewed
- Topology
- From to’s and pin Pairs for (Timing rules)
- Formulas
- Differential Pairs
- Parallelism (crosstalk) Entering rules by example
- Entering rules based on practical examples
- Termination
- Constraints of a DRR2
- Creating and using templates
- Some other stuff
- Comments
- Roll back
- Room property
What You Will Learn
- Use CES standalone, from within the frontend, or modified in the backend. And how this all is synchronized in the flow
- Partition de design based on physical as well as electrical design needs
- Differentiate between electrical and physical nets and there design criteria
- Experience the other worlds demands. Meaning for an electrical engineer to see why the layout engineer protests against the requested needs. While the layout engineer is explained the way an electrical engineer makes these requests. And where both parties need to cooperate in an early stage of the design
- How CES provides the electrical engineer a way to control how correct his constrained are implemented in the Layout and were the implementation is close to the max/min constrained Value. (Delegation is good, control is better)
- How to enter and reuse previous results with templates
Who Should Attend
- Engineers who create schematics that will be used as "front end" designs for Mentor’s Expedition PCB layout tool
- PCB Designers who would like to have a good understanding of the constraining Process