Meeting the Challenges of DDRx Design
On-demand Web Seminar
Abstract
Learn the differences between DDRx standards and how to use HyperLynx to validate your DDRx system timing.
Duration: 25:28
Details
Overview
During webcast, we’ll cover some of the basic electrical requirements of DDR2/DDR3 interfaces, show you how to meet the timing and signal integrity (SI) requirements of these memory interfaces, and provide tips on developing these memory subsystems.
Included will be a HyperLynx demonstration that shows how quickly and easily you can analyze DDRx interfaces for SI and timing issues.
DDR2 and DDR3 (Double Data Rate) have become the dominant memory standards for high-bandwidth applications, yet developing proper routing constraints and meeting set-up and hold times can be a challenge.
About the Presenter
Steve McKinney
Steven McKinney is a business development manager for Mentor Graphic's Board System Division where he supports Mentor's PCB analysis technologies which include tools for Signal Integrity, Power Integrity, Thermal and EMC design. Steven has previously held roles in technical marketing at Mentor Graphics, specializing in signal integrity and EMC analysis tools and educating the engineering community on signal integrity, power integrity, and EMC design issues. Prior to working for Mentor, Steven was a signal integrity engineer at Dell Computer developing server hardware. Steven received his BSEE and MSEE from North Carolina State University.
What You Will Learn
- The differences between the DDRx standards
- Electrical requirements of DDR2 and DDR3
- How to develop a DDR memory subsystem
- How to use HyperLynx to validate your DDRx system timing
Who Should Attend
- Engineers and Managers designing high-speed memory systems
- Hardware Engineers, Signal Integrity Engineers, and PCB Designers, regardless of EDA tools currently used
- Current HyperLynx customers interested in DDRx applications (call for special DDRx upgrade pricing!)
Related Resources
Multimedia
3D modeling methods in SERDES Designs: Is via behavior causing your SERDES designs to fail?
Learn how to evaluate vias through 3D EM Simulation and Post-Route Verification to validate via behavior and its effects on multi-gigabit channels.…View On-demand Web Seminar
Analyze and Stop Via Coupling Noise
Learn the causes of noise from via coupling through power planes, how to simulate the interaction of vias and power planes and discover quality design practices for single ended vias.…View On-demand Web Seminar
PCB Crosstalk Fundamentals - What It Is and How You Can Prevent It
Crosstalk is an abstract concept that can cause very real design failures, which can be difficult to reproduce, debug, and resolve. You will learn the basics of PCB crosstalk, including terminology, mathematical...…View On-demand Web Seminar
Other Related Resources
High Speed PCB Layout: Physical Design Issues of Highspeed Interfaces
White Paper: Moore’s law, applied to data rates, has pushed PCB circuits so fast that the layout becomes part of the circuit. In designs such as DDR3 and PCIe, the fastest memory and high-speed serial performance...…View White Paper
Understanding Via Effects
White Paper: As the demand for fast computation and information transmission has increased dramatically in recent years, many designs have boards with signals operating in the multiple-Gbps range. Advanced memory designs...…View White Paper
Analyzing Crosstalk's Impact on BER Performance: Methods and Solutions
White Paper: This paper discusses two major issues associated with channel crosstalk that have not been fully addressed previously: models from measurements and algorithms for BER prediction. It presents a practical...…View White Paper