Meeting the Challenges of DDRx Design
On-demand Web Seminar
During webcast, we’ll cover some of the basic electrical requirements of DDR2/DDR3 interfaces, show you how to meet the timing and signal integrity (SI) requirements of these memory interfaces, and provide tips on developing these memory subsystems.
Included will be a HyperLynx demonstration that shows how quickly and easily you can analyze DDRx interfaces for SI and timing issues.
DDR2 and DDR3 (Double Data Rate) have become the dominant memory standards for high-bandwidth applications, yet developing proper routing constraints and meeting set-up and hold times can be a challenge.
About the Presenter
Steven McKinney is a business development manager for Mentor Graphic's Board System Division where he supports Mentor's PCB analysis technologies which include tools for Signal Integrity, Power Integrity, Thermal and EMC design. Steven has previously held roles in technical marketing at Mentor Graphics, specializing in signal integrity and EMC analysis tools and educating the engineering community on signal integrity, power integrity, and EMC design issues. Prior to working for Mentor, Steven was a signal integrity engineer at Dell Computer developing server hardware. Steven received his BSEE and MSEE from North Carolina State University.
What You Will Learn
- The differences between the DDRx standards
- Electrical requirements of DDR2 and DDR3
- How to develop a DDR memory subsystem
- How to use HyperLynx to validate your DDRx system timing
Who Should Attend
- Engineers and Managers designing high-speed memory systems
- Hardware Engineers, Signal Integrity Engineers, and PCB Designers, regardless of EDA tools currently used
- Current HyperLynx customers interested in DDRx applications (call for special DDRx upgrade pricing!)
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