DFM Verification for PCB Assembly
On-demand Web Seminar
Abstract
The assembly of a printed circuit board is typically the most expensive part of the manufacturing process. Not only are the components associated with the PCB expensive, but any errors not found until PCB assembly can mean the scrapping of the PCB itself if layout changes are required.
Duration: 27:43
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Overview
The assembly of a printed circuit board is typically the most expensive part of the manufacturing process. Not only are the components associated with the PCB expensive, but any errors not found until PCB assembly can mean the scrapping of the PCB itself if layout changes are required. Mentor Graphic's vSure DFM verification solution identifies manufacturability issues concurrent with your design process, effectively performing a virtual prototype of your design. This greatly reduces the number of revision spins it takes to reach your volume and quality objectives. This session will include an EMS company's perspective and a product demonstration.
What You Will Learn
- Common fabrication issues that result in frequent board re-spins
- Checks you can use to optimize yield and minimize board cost
- How to adopt a repeatable DFM validation process, concurrent with your layout design
About the Presenter
Patrick McGoff
Mr. McGoff recently joined Mentor Graphics through the Valor acquisition. After joining Valor in 1996, Mr. McGoff held various sales and sales management positions within the company, including VP Design Market, VP of Sales for North America, VP of Sales for China and Director of Sales, Strategic Accounts. Mr. McGoff has a Bachelor of Business Administration degree in Marketing from Georgia State University (1979), USA. Prior to joining Valor, Mr. McGoff was the Eastern Regional Sales Manager for Gerber Scientific Instruments, and later managed the North American sales for Valor and Orbotech’s joint venture company, Frontline PCB Solutions.
Who Should View
- Common assembly issues that result in frequent board re-spins
- Checks that can be performed to optimize yield and minimize assembly costs
- How to adopt a repeatable DFM validation process concurrent with your layout design
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