Eliminate Costly Delays for Chip on Board and MCM-L Designs

Overview

Manually creating Bare Die or wire bonds for your MCM-L designs is an error-prone and time-consuming process that can lead to expensive redesigns and delays in getting products to market. PCB library creation for die components alone can take several hours. Automating the process can help.

In this PADS design webinar we’ll explore automated techniques for removing these errors, creating die components, and meeting your design schedule goals. We'll show you how to find the best solution for your bare-die design through 'what-if' analyses that maximize yield and ensure fit while minimizing design size.

What You Will Learn

• How PADS can automatically generate substrate bond pad and wire bond rules
• How easy it is to study feasibility, change rules, and instantly see results
• How PADS can complete Multi-Chip design with conventional or Blind/Buried Vias
• How to generate die components with GDSII files

Who Should View

• Electrical engineers responsible for the entire PCB design process
• PCB designers working with Bare Die for chip-on-board and MCM-L designs
• PCB design specialists