HyperLynx: Signal Integrity Analysis for any User in any Design Flow
On-demand Web Seminar
In this webinar you will see why HyperLynx is extremely effective in any design flow. You will learn how easy it is to take your layouts into the HyperLynx simulation environment. You will learn three SI checks you can easily add to your process to improve product quality.
Are you trying to improve product reliability or reduce design cycle time? Do you own PCB simulation tools that sit idle because they are too difficult to use?
If you are interested in an easy-to-use and accurate simulation tool, then attend this webinar to learn how HyperLynx will dramatically improve your design flow. You will learn why HyperLynx is so popular and how you too can cash in on the quick time-to-results possible with this tool suite. The focus of this session is on signal integrity simulation but HyperLynx also offers solutions for thermal, power integrity and analog simulation.
In this webinar you will see why HyperLynx is extremely effective in any design flow. You will learn how easy it is to take your layouts into the HyperLynx simulation environment. You will learn three SI checks you can easily add to your process to improve product quality. Enable yourself with a simulation using an innovative tool built for layout designers and SI experts alike. Whether your pain point is design reliability or cycle-time reduction, simulation will significantly reduce your pain and increase your design confidence.
What You Will Learn
- Signal Integrity basics
- Where HyperLynx fits in your design process
- How HyperLynx works with non-Mentor Graphics design flows
- How to develop intelligent and effective routing constraints
- How to quickly verify your routing in a batch mode simulation
- Available HyperLynx packaging
About the Presenter
Andrea Fox is a Field Application Engineer at Mentor Graphics. For the past eight years Andrea has held AE roles at Mentor Graphics focused on PCB engineering and high speed analysis tools. Andrea holds a MS in Engineering Management from Portland State University and a BS EET from Western Washington University.
Who Should View
- Project Managers
- Design Engineers
- Board Designers
- Engineering Managers
Learn how to evaluate vias through 3D EM Simulation and Post-Route Verification to validate via behavior and its effects on multi-gigabit channels.…View On-demand Web Seminar
Learn the causes of noise from via coupling through power planes, how to simulate the interaction of vias and power planes and discover quality design practices for single ended vias.…View On-demand Web Seminar
Crosstalk is an abstract concept that can cause very real design failures, which can be difficult to reproduce, debug, and resolve. You will learn the basics of PCB crosstalk, including terminology, mathematical...…View On-demand Web Seminar
Other Related Resources
White Paper: Moore’s law, applied to data rates, has pushed PCB circuits so fast that the layout becomes part of the circuit. In designs such as DDR3 and PCIe, the fastest memory and high-speed serial performance...…View White Paper
White Paper: As the demand for fast computation and information transmission has increased dramatically in recent years, many designs have boards with signals operating in the multiple-Gbps range. Advanced memory designs...…View White Paper
White Paper: This paper discusses two major issues associated with channel crosstalk that have not been fully addressed previously: models from measurements and algorithms for BER prediction. It presents a practical...…View White Paper