Multi-GHz Channel Analysis Using HyperLynx and Xilinx' IBIS-AMI Models Web Seminar

Overview

Comprehensive analysis of multi-GHz SERDES links with HyperLynx and the Xilinx V5 AMI design kit enables designers to make the tradeoffs needed to attain cost-effective and robust SERDES channel designs.

During this webinar we will investigate important aspects and key features of accurately analyzing multi-GHz SERDES links (such as PCIe 2.0) with IBIS AMI models in HyperLynx. These include:

• The importance of an accurate time-domain characterization of the channel.
• HyperLynx's patent-pending adaptive worst-case bit sequence with AMI models and its impact on stressed eye density plots and bit error rate (BER) results.
• Fast channel simulation techniques with HyperLynx FastEye that allow you to quickly ensure optimal link performance within a range of conditions.
• The impact of the Power Distribution Network (PDN) on differential via behavior and BER performance.

We will also present a high-level overview of the Mentor design kit for Xilinx V5 high-speed I/O transceivers. The kit includes integrated support for IBIS AMI as well as advanced tools for eye margin analysis and advanced results-viewing capabilities.

What You Will Learn

• The new IBIS 5.0 AMI modeling methodology for SERDES
• How HyperLynx supports Xilinx IBIS-AMI Models
• How to identify key features for accurate analysis of multi-GHz SERDES links with IBIS AMI models in HyperLynx
• The impact of the PDN on differential via behavior and BER performance

Who Should View

• Systems designers who are adding high-speed serial links (e.g., PCIx, SATA-II) to their designs
• Electrical engineers concerned with high-speed PCB design issues
• Engineers facing SERDES design challenges
• Anyone considering Xilinx Virtex-5
• Signal integrity engineers
• HyperLynx customers interested in multi-GHz applications