PADS I/O Designer Demo
Requires Flash Player.
This demo shows how I/O Designer can help reduce design time and make the physical FPGA on board integration a concurrent and automated process. Using I/O Designer in the process and iterating between the FPGA and PCB design flows enables the designers to focus on performance optimization and minimizing the manufacturing costs. I/O Designer makes sure the FPGA and PCB design flows are automatically kept in sync.
Duration: 22:09
Tags: Design Creation
Products: PADS
View Product Demo (Opens in New Window/External URL)
Related Resources
Multimedia
The Engineers Desktop, Room for Improvement?
With Electronic product design increasing functionality whilst decreasing form factors, Electronic Engineers experience pressure to reduce development time, increase productivity, optimize costs without...…View On-demand Web Seminar
Enterprise-level FPGA-on-Board Optimization Strategies
This session will showcase how pin optimization technology streamlined into a component management and design flow can realize schedule and cost benefits throughout the enterprise.…View On-demand Web Seminar
OrCAD to DxDesigner Conversion Demonstration
This video demonstrates how to use DxDesigner to load, translate, and import an OrCAD schematic for use in PADS Layout.…View Product Demo
Other Related Resources
Agilent Technologies
Success Story: Agilent reduced typical 4-8 week times to layout one FPGA to 1-2 weeks using I/O Designer.…View Success Story
Leveraging FPGA in PCB System Designs
White Paper: FPGA devices create compelling business drivers generating a tidal wave of FPGA adoption for the implementation of system PCB designs. Obviously, the time to market advantages and capacity/performance characteristics...…View White Paper
Getting Started in HDI Fabrication
White Paper: High-density interconnect (HDI) fabrication is the fastest growing segment of the printed circuit industry. From its simple start in 1985 for Hewlett-Packard's first 32-bit computer (the Finstrate) to today's...…View White Paper
Test-drive the full version of HyperLynx PI in this hands-on virtual lab:
- Use PDN Editor for exploratory power integrity analysis
- Use BoardSim to complete a DC drop analysis
- Meet target impedance goals based on stackup design, capacitor selection and capacitor mounting structures
- Data files and PDF exercise guides for 3 lab exercises:
- DC drop and current density analysis
- Plane noise analysis
- Decoupling analysis
- 7-day access to a full, working virtual copy of HyperLynx PI
- Anytime, anywhere access to your
virtual lab

