What Engineers Need to Know about SERDES, SPICE, and IBIS-AMI
Requires Flash Player.
For those wanting to validate bit error rates down to 10^-12 and 10^-15 on busses like SATA and PCI-Express, traditional simulation techniques using SPICE models won’t work. This 15-minute webinar discusses the new simulation and modeling techniques for SERDES busses, including FastEye™ Channel Analysis, S-parameter simulation, frequency-dependent loss modeling including surface roughness, and VHDL-AMS and IBIS-AMI models.
Duration: 14:37
Tags: Circuit Simulation
Products: HyperLynx
View Technology Overview (Opens in New Window/External URL)
Related Resources
Multimedia
SERDES Design: Is via behavior causing your SERDES designs to fail?
Learn how to evaluate vias through 3D EM Simulation and Post-Route Verification to validate via behavior and its effects on multi-gigabit channels.…View On-demand Web Seminar
Analyze and Stop Via Coupling Noise
Learn the causes of noise from via coupling through power planes, how to simulate the interaction of vias and power planes and discover quality design practices for single ended vias.…View On-demand Web Seminar
PCB Crosstalk Fundamentals - What It Is and How You Can Prevent It
Crosstalk is an abstract concept that can cause very real design failures, which can be difficult to reproduce, debug, and resolve. You will learn the basics of PCB crosstalk, including terminology, mathematical...…View On-demand Web Seminar
Other Related Resources
Analyzing Crosstalk's Impact on BER Performance: Methods and Solutions
White Paper: This paper discusses two major issues associated with channel crosstalk that have not been fully addressed previously: models from measurements and algorithms for BER prediction. It presents a practical...…View White Paper
Improving Characterization of Serial Links by Dynamic Deconvolution from PRBS Responses
White Paper: Predicting and understanding the performance and the limiting factors of a serial data link is critical to high speed serial design process. To this end we concerned ourselves with characterization of active...…View White Paper
Predicting BER to Low Probabilities: Validating of a New Analysis Methodology
White Paper: This paper has detailed a methodology illustrating how IBIS AMI models can be used in combination with Mentor’s analysis tools to attain very low BER level’s with a high level of confidence...…View White Paper
Test-drive the full version of HyperLynx PI in this hands-on virtual lab:
- Use PDN Editor for exploratory power integrity analysis
- Use BoardSim to complete a DC drop analysis
- Meet target impedance goals based on stackup design, capacitor selection and capacitor mounting structures
- Data files and PDF exercise guides for 3 lab exercises:
- DC drop and current density analysis
- Plane noise analysis
- Decoupling analysis
- 7-day access to a full, working virtual copy of HyperLynx PI
- Anytime, anywhere access to your
virtual lab