PADS High-Speed Design

Details

Overview

This seminar will show you how PADS 9.0 can help you quickly and accurately design high-speed circuits. PADS Design Solutions improve high speed design efficiency by combining the industry's most popular EDA tools in an easy-to-use, integrated flow. In this seminar we will cover tools to help:

  • Define high-speed design constraints.
  • Capture high-speed rules for layout within the schematic tool
  • Interactively use the auto routing tools to route high-speed nets according to engineering rules
  • Verify that the routed high speed nets will perform as specified

What You Will Learn

  • How PADS tools can help analyze high speed designs before and after layout
  • How PADS tools can simplify routing high speed nets to meet design constraints

About the Presenter

Presenter Image Sherwin Davenport

Sherwin is a Sr. Application Engineer for the PCB products at Mentor Graphics Corp. His career in electrical design and analysis has spanned over 19 years, with roles including Electrical Technician, Signal Integrity Engineer and Application Engineer.

Sherwin received his Electrical Engineering degree at Brigham Young University.

Who Should View

  • Electrical engineers
  • Layout designers
  • Signal Integrity (SI) engineers

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