PCI Express Basics: Developing Physical Design Rules for PCIe
On-demand Web Seminar
This webinar explores the PCI Express (PCIe) specification and how physical design elements of PCIe impact electrical performance. Topics covered Include how to use HyperLynx to generate design rules for routing and routing considerations for successful design of interfaces that conform to the PCI Express specification.
Did you know that there are well over 30 electrical design requirements identified by the PCI Express (PCIe) specification? Ensuring design robustness requires careful planning, and a thorough understanding of your design's electrical behavior. This webinar looks at the some of the most critical electrical performance requirements that PCB designs must meet to comply with the standards for the PCIe Gen1 and Gen2 specification. We will also highlight what’s to come in Gen3.
We’ll explore some of the key physical design elements that impact electrical performance, such as: trace geometries, vias, and reference plane discontinuities using HyperLynx SI and PI in both the time and frequency domain. These will help you better understand the principles needed to successfully develop a PCIe interface.
What You Will Learn
- Electrical design requirements for PCIe Gen1, Gen2, & Gen3
- How to use HyperLynx to generate physical design rules for routing
- Routing considerations for successful design of PCIe interfaces
Who Should Attend
- Hardware engineers working on PCIe designs
- Signal Integrity engineers developing routing constraints
- PCIe Card and System designers
About the Presenter
Steven McKinney is a business development manager for Mentor Graphic's Board System Division where he supports Mentor's PCB analysis technologies which include tools for Signal Integrity, Power Integrity, Thermal and EMC design. Steven has previously held roles in technical marketing at Mentor Graphics, specializing in signal integrity and EMC analysis tools and educating the engineering community on signal integrity, power integrity, and EMC design issues. Prior to working for Mentor, Steven was a signal integrity engineer at Dell Computer developing server hardware. Steven received his BSEE and MSEE from North Carolina State University.
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