Power Integrity Analysis in the PADS Flow
On-demand Web Seminar
In this webinar, you will learn about simulating Power Integrity in the PADS flow.
This includes looking at power planes and stitching vias to ensure minimal DC voltage drop and current density, as well as looking at the AC effects of decoupling capacitors, VRMs, power planes, and board stackup.
What You Will Learn
- How to analyze and solve issues with DC Drop -How to analyze and solve issues with decoupling
- How to design a board to meet all power integrity and cost requirements
About the Presenter
Patrick Carrier worked as a Signal Integrity Engineer at Dell for 5 years before joining Mentor in September 2005. Patrick is now a technical marketing engineer specializing in analysis products, including signal and power integrity, EMC, and thermal design.
Who Should View
- Anyone designing PCBs with power-hungry ICs
- Anyone with more than 2 voltage rails on their PCB design
- Anyone wanting to reduce cost by removing layers, capacitors
- Anyone concerned about Power Integrity
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