Bringing SERDES Simulations to the Next Level with Mentor's Fast Eye Technology
On-demand Web Seminar
In this 30-minute web seminar, you will learn how Mentor's Fast Eye technology is changing the way SERDES busses are simulated, allowing for validation of channel performance down to the 1e-15 BER level and beyond. Learn More About HyperLynx and SERDES Design.
The low BER requirements of high-speed differential signalling on busses such as PCI Express, SATA, and FibreChannel have brought about the need for exhaustive eye diagram analysis. Traditional methods of time-domain simulation are impractical for verifying BER requirements of 1e-12 and lower. Fast Eye from Mentor Graphics solves this problem by providing such eye diagrams in hours instead of days or weeks of simulation. We will discuss the methods used to generate the simulation data, including prediction of the worst-case bit sequence on the channel.
In this 30-minute web seminar, you will learn how Mentor's Fast Eye technology is changing the way SERDES busses are simulated, allowing for validation of channel performance down to the 1e-15 BER level and beyond.
What You Will Learn
- How Fast Eye generates exhaustive eye diagrams orders of magnitude faster than traditional time-domain analysis
- How to use Fast Eyes from within HyperLynx
- The features, capabilities, and benefits of Fast Eye Diagram analysis
Who Should View
Hardware Engineers, Signal Integrity Engineers, and PCB Designers who:
- Are designing with SERDES busses such as PCI Express
- Want to analyze and verify multi-gigabit interfaces
- Need to validate their designs at very low BER (bit error rates).
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