PADS Layout

RF Design

RF design brings new challenges to PCB Design Engineers including: the ability to handle complex copper shapes and import simulator-generated DXF files of RF/Microwave geometries.

PADS allows engineers to create wireless designs such as cell phones, cell repeater stations, satellite communication, automotive FOBS and any other RF/Microwave application.

With PADS Layout:

• Import complex copper shapes and line geometries into the Decal Editor
• Shield crucial traces for efficient channel/co-planar waveguide design
• Stitch area with Vias Arrays for complex copper-pour areas with specific pattern requirements
• Provide greater conductivity between planes on different layers
• Minimize noise susceptibility
• Create precise outlines and square & chamfered corner geometry and output them in Gerber

Overview

The PADS Layout solution combines ease of use with great value and broad technology, making it ideal for complex PCB designs

PADS Layout is a rich, robust PCB editing environment that provides all the functionality needed to efficiently design and route complex PCBs. PADS Layout starts with netlist import, reading in all the component and netlist information, component attributes, design rules, and net constraints defined in the schematic.

A wizard-driven, shape-creation tool simplifies library component creation and generates accurate land patterns. Component placement is easy and precise, using a combination of manual and automatic tools that allows group placement and component rotation down to a tenth of a degree.

PADS Layout also provides a robust set of manual and interactive routing tools. Newest among these is PADS® Router, the shaped-based, any-angle route editor that gives you full control and superior interactive routing in real time.

PADS AutoRouter

PADS AutoRouter maximizes routing quality with constraint-driven routing and automatic design rule checking

PADS AutoRouter ships with every seat of PADS Layout. This powerful, shape-based autorouter combines high completion rates with minimal post-route rework for the highest yields possible. Native any-angle and diagonal routing algorithms accurately and efficiently route high-density designs.

Tight integration with PADS Layout ensures that PADS AutoRouter follows design rules and net constraints entered at the schematic or PCB level, minimizing post-route checking. With PADS AutoRouter you get:

• "Push and shove" and "rip-up and retry" technology for batch-routing results that rival interactive routing in design quality and aesthetics
• A combination of pad-entry controls, same-net clearance rules, and copper sharing that can meet fabrication requirements automatically
• Integrated testpoint routing and post-route auditing to adapt to your existing design-for-test (DFT) process
• True diagonal routing that minimizes trace lengths and design layers

Automation

Automation methods allow you to query and modify PADS Layout data structures for better communication with other applications

PADS Layout combines Object Linking and Embedding (OLE), automation methods, and a Visual Basic engine to provide advanced integration and customization. Extended API commands provide direct access to PADS Layout data structures for faster, better communication between all your design tools.

• With PADS Layout, you can: Cross-probe between data elements with applications, such as Microsoft® Excel®
• Leverage other EDA and OLE-compliant tools to enhance your design process
• Use a Script Wizard to take advantage of automation techniques, even if you don’t have any programming background

Split Plane Definition

Split/Mixed-Plane operations ensure connectivity to multiple plane areas

Split/Mixed-Plane operations provide an interactive and automated method for creating complex embedded planes and routes.

• Automatically check connectivity to multiple split-plane areas, ensuring an electrically correct design
• Maintain all design rules, including net-specific and conditional net rules
• Simplify the separation of embedded planes into multiple plane polygons
• Support embedded traces on internal plane layers
• Support positive and negative plane areas

Physical Design Reuse

To minimize errors, PDR allows you to replicate ‘golden circuits’ in new and existing designs

The Physical Design Reuse (PDR) option supports the creation, saving, and placement of physical reuse elements independent of the schematic source. By allowing you to reuse existing, proven circuits, PDR significantly reduces design time.

• Save completely routed circuits as reuse elements in a PDR library
• Easily replicate reuse elements to support multi-channel designs, whether the design is newly created or taken from the PDR library
• Use intelligent, element-building technology to create a clone of the initial reuse element and position it on your cursor for placement

Design For Fabrication

With DFF Audit, you can find and fix all rule violations prior to fabrication

Verify your designs with DFF Audit. With this module you can perform a variety of fabrication design rule checks. Fabrication errors detected by DFF Audit are corrected in PADS Layout so you don’t have to worry about errors being corrected at the fab house and never updating your design.

• Identify and correct issues that could cause fabrication problems, without ever leaving the PADS Layout environment
• Check for acid traps, copper slivers, soldermask slivers, traces in a soldermask opening, detection of silkscreen over pads, and more

Design for Test

DFT Audit reduces costly design iterations and ensures the testability of your designs before fabrication

DFT Audit provides two key functions: testpoint assignment and reporting.

• Testpoint Assignment: By enabling the testpoint function in PADS AutoRouter, DFT Audit inserts testpoints during normal route passes, converting existing vias and pads to testpoints, or adding necessary testpoints based on your rules. PADS AutoRouter an even be instructed to perform iterative passes with decreasing pad sizes, thus maximizing testpoint coverage.
• Testpoint Report: At any time, a comprehensive testpoint coverage report can be generated for design review.

DxDesigner Link

Integration between DxDesigner and PADS Layout includes crossprobing for intuitive component placement and easy identification of critical nets

Provides push-button integration between PADS Layout and DxDesigner™, allowing you to:

• Pass netlists and attributes bidirectionally for seamless schematic-to-layout design synchronization
• Cross-probe between schematic and layout, for intuitive component placement according to schematic flow and for easy identification of critical nets for design reviews

Other Features

Autodimensioning - PAD Layout includes robust dimensioning tools that document the PCB form factor automatically. These tools include datum and standard dimensioning, radius, angle, and leader support, as well as user-defined tolerancing.

Online DRC Design Rule Checks - DRC enable base and extended rules hierarchy, including layer, class, group, pin pair, and conditional rules. Four modes of operation (prevent, warn, explain, allow) let you choose the degree of system assistance you want as you route.

Analog Design - The Analog Tool Kit enables automatic and interactive jumper capabilities and advanced teardrop and pad-filleting controls for high-density, single- and double-sided boards. By automating a tedious, manual process, the Analog Tool Kit saves time and helps ensure that placements will meet your design rules and requirements.

Advanced Rule Set (ARS) – Extends the hierarchy of base design rules to include layer, class, group, pin pair, conditional, and differential-pair rule settings. Measures and verifies signal requirements for high-speed layout based on signal routing and board stack-up. ARS is required for PADS Router and PADS AutoRouter.

IDF Link – Allows 2D physical information to pass via an IDF file to and from PADS Layout and mechanical engineering tools such as Pro/ENGINEER® and SolidWorks.

CAM Outputs- The PCB Editor provides CAM utilities to output DirectCAM, drill data, Gerber, and other standard data-exchange formats.