PADS Options

The Advanced Packaging Toolkit can significantly reduce package design time for PADS Layout users who work with bare-die components such as single- and few-chip modules and chip-on-board. The Advanced Packaging Toolkit improves design quality by automating key aspects of the advanced package design process, including die capture, rules- based wire bond design, flip-chip definition, and report generation. This option aids in the routing of single-chip packages and the definition of die flags. A variety of die, die flag, and route wizards and tools speeds design reuse and creation of manufacturing data.

With the Advanced Rules (ARS) option, you have the industry's most comprehensive hierarchical rule set available on the market today. This option extends the basic rules to include:

• Expanded rules hierarchy
  Layer, net class, pin pair, pin pair groups, component, decal
• Added rules for differential pairs
  Gap, min/max length, matched length
• Added conditional rules between objects
  Class to class, class to net, etc.
• Component pad entry rules
  Clearances, fanout patterns, and more
• Verification of fast circuit design
  Crosstalk, signal delay, stub control, and more
• Batch verification of capacitance and impedance

Integration and cooperation between the ECAD and MCAD departments is more important than ever. PADS Collaborator, using the ProSTEP schema, allows the passing of full or incremental data between PADS and mechanical CAD tools. Proposed changes can be reviewed, and either accepted or rejected, adding a new level of cooperation and collaboration between the two groups, helping reduce the overall design cycle time.

DFM Analysis enables PCB design teams to validate that a design is prepared for manufacturing directly within the PADS environment. Regardless of the complexity of their designs, design teams are continuously challenged with getting products into volume production to reach the market quickly. Manufacturers alone cannot identify all production obstacles; PCB designers must play an earlier role in validating the layout of a design by considering key aspects of fabrication and assembly that directly impact manufacturability.

The DFM Analysis incorporates more than 100 of the most valuable fabrication and assembly related analyses. Examples of issues identified by DFM Analysis include resist slivers, unintended copper exposed by soldermask, and testpoint-to-testpoint spacing, all of which delay production. Identifying and solving these issues early in layout, and long before manufacturing, saves costs and brings the product to market much quicker.

DFT Audit is a design-for-test (DFT) option for PADS® Layout. Based on test point coverage rules that you define, DFT Audit will analyze the design, create and automatically place test points, and verify all your rules have been met.

DFT Audit uses tools specifically developed for programming in-circuit test equipment. This guarantees 100% testability for all nets on your board and helps ensure accurate testability prior to fabrication, thus saving time and money from being spent on needless prototypes. The result is decreased time to market and improved design performance.

Designing with FPGA’s can add complexity and time to the design cycle. With I/O Designer for PADS, complex fractured symbols can automatically be created. By understanding the internal architecture of the FPGA, I/O Designer can “unravel” or swap pins to optimize the FPGA on the PCB, and improve the routability of the device.

Creating design variants, rather than having compete, separate schematic and layout databases, can save time and money. Variant Manager for PADS allows the definition of multiple design variants by installing, uninstalling, and/or substituting parts for each variant. Variants created in DxDesigner are seamlessly passed to PADS Layout. Variant Manager for PADS allows variant based output of parts lists, and final board documentation.