High speed digital drivers need a good source of power to produce clean, fast signals. For a driver to switch the state of a signal in tens or hundreds of picoseconds, the power plane must be able to supply significant current over a wide bandwidth. The surge in current creates voltage fluctuations in the power distribution network (PDN) that appear as noise at the power pins of the drivers. This plane noise is then transferred through the driver to the signal that is being driven onto a transmission line. Power integrity analysis tools can provide an impedance profile of the PDN in the frequency domain, and a noise profile of the PDN in the time domain, but it is also useful to see the effect that the noise at the power pin of an IC has on the resulting output signal quality. By extracting a model of the power plane, a simulation can be run using SPICE models for drivers and receivers, revealing the PDN noise effects on the transmitted signal.