Understanding Via Effects

ABSTRACT

As the demand for fast computation and information transmission has increased dramatically in recent years, many designs have boards with signals operating in the multiple-Gbps range. Advanced memory designs are targeting over 10 Gbps data rates while the SERDES standard is moving toward 25-28 Gbps. With the signal speed changes come the new challenges of solving design issues never seen before. The electrical components of signal paths on boards and interconnects present problems, such as significant dielectric loss or impedance discontinuity from non-trace portion, which used to be ignored at lower signal speed. For a typical SERDES channel (Figure 1), the discontinuity contribution comes from the vias for signal switching layers, connectors enabling multi-board connections, and packages. To PCB designers, only via configurations are under their control in these discontinuity contributors.