PCB Design Software Success Stories

Utilitek Systems, Inc.

Johnson Controls Utilitek exploited the concurrent design capabilities of Mentor Graphics Expedition Enterprise tools to design two complex boards in a shortened timeframe. View Success Story

Finisar

 Finisar has been pushing PADS performance to the limit for twenty years, and they’re still impressed. View Success Story

Hughes Network Systems

Hughes Network Systems Mentor Graphics ICX provides an advanced design and verification environment for even the toughest of Hughes' high-speed challenges. View Success Story

Johnson Controls

Johnson Controls Expedition Enterprise integrates and manages the system design flow, enabling seamless data transfer and improved designer productivity and performance, all while facilitating communication with the corporate... View Success Story

Nanya Technology

Mentor Graphics HyperLynx Pl and SI tools helped Nanya Technology engineers correct an intermittent reference design problem in the company's DRAM technology. View Success Story

Alcatel-Shanghai Bell

Alcatel-Shanghai Bell gave their design team seven weeks to complete a project estimated to require thirteen. The solution: the concurrent design capabilities of Mentor’s Xtreme PCB. View Success Story

L-3 Communications

L-3 Communications needed to design a very complex PCB, but could they do so with their existing Expedition Enterprise system? View Success Story

SeaMicro

SeaMicro discovered voltage drop problems on their PCB; HyperLynx PI quickly locates these issues. View Success Story

Waters Corporation

Waters Corporation logo Through a substantial evaluation program, Waters reviewed their PCB design tool requirements and decided that Expedition Enterprise provided the precise solution they had been seeking. View Success Story

Broadcom Corporation

Broadcom uses I/O Designer to develop PCB with multiple FPGAs and beats the project schedule by 66%. View Success Story

Agilent Technologies

Agilent Technologies Agilent reduced typical 4-8 week times to layout one FPGA to 1-2 weeks using I/O Designer. View Success Story