Agilent faced a complicated PCB design incorporating eleven 1148-pin FPGAs. Using I/O Designer for the first time, they tackled the problem and saved 40% over the time budgeted for the project.
“Our success with I/O Designer on this project has convinced us to deploy the tool as a world-wide Agilent standard for FPGA schematic entry.”
Agilent Uses I/O Designer
product overview: I/O Designer offers a unique process for moving through the design flow, from the top level HDL description to the PCB level symbol, as well as to the physical pin information necessary for the FPGA place and route tools.
When faced with a design using eleven 1148-pin FPGAs — each having a complex set of constraints — Agilent decided it was time to adopt a new tool, and a new methodology for the design. The new tool needed to facilitate cooperation between FPGA designers and the PCB designers. The tool Agilent chose to best handle the problem was Mentor Graphics I/O Designer (IOD).
Based on previous experience, they estimated that each FPGA would require 4-8 weeks just for I/O pin assignment. However, using I/O Designer — for the first time — they were able to complete each FPGA in just 1-2 weeks…an incredible reduction in time of 75%. But, there savings reached further than just the FPGA pin assignment and layout.
Because of the adoption of IOD, they developed a new product design strategy based on hierarchy, which resulted in time savings in other areas of the design as well. The entire project, from schematic to complete layout, took 10 months: one-third less time than budgeted!
“This board was the right problem at the right time for the tool [I/O Designer] and the FPGA's.”