PCB Technical Publications

This document describes of the advantages of deploying HyperLynx to meet the increasingly complex challenges of high speed channel design. An overview is provided of the advanced analysis technology. Finally two case studies are presented exploring the sensitivity of channel design to two design trade-offs: via back-drilling and trace length imbalance.

The design of high performance multi-Gbps channels inevitably requires facing new challenges. One possible approach is to attempt to blindly apply conservative layout guidelines that have been established by the success of previous designs or have been provided in the form of reference designs from an IC vendor. This methodology has merit, but will tend to result in designs that have mediocre performance and require unnecessarily expensive PCB materials and manufacturing processes and/or over-constrain the layout engineer placing components and routing the PCB. An alternative approach that will reduce cost and allow maximum performance is to develop knowledge of how physical design rules affect electrical performance so that appropriate tradeoffs can be applied.

HyperLynx GHz provides an intuitive but powerful suite of tools that allows every member of the high speed serial channel design team to participate in creating the highest quality design while minimizing manufacturing costs. HyperLynx GHz also provides the post layout analysis tools that allow the team to ensure design goals have been met and that the product will operate reliably under field conditions.

The signal channels that link high speed processors to memory and various other peripherals, are limited by the inherent characteristics of the printed circuit board. These are what ultimately connect information to the outside world. One limiting factor is the effect of nonuniformity of the glass fiber distribution in the printed circuit substrate material, also known as fiber weave effect (FWE). FWE introduces signal skew and timing errors which place an upper limit on bit rate and trace length.

High Density Interconnect (HDI) is being used more often to meet the growing need for more complex designs in smaller form factors. Beyond some of the more obvious electrical effects of using smaller vias, there is also an impact to the power integrity of a board using HDI. This includes different effects of mounted inductances of decoupling capacitors, changes in plane performance due to reduction in perforation from chip pinouts, and the inherent plane-capacitance changes from using dielectrics of various thicknesses. This paper will examine and quantify these effects, using numerous design examples, including a large conventional through-hole design board that was reduced using HDI.

For advanced signaling over high-loss channels, designs today are using equalization and several new measurement methods to evaluate the performance of the link. Both simulation and measurement tools support equalization and the new measurement methods, but correlation of results throughout the design flow is unclear. In this paper a high performance equalizing serial data link is measured and the performance is compared to that predicted by simulation. Then, the differences between simulation and measurements are discussed as well as methods to correlate the two.

Mixed RF, analog and digital technology boards are becoming commonplace in many industries including wireless telecom, consumer, automotive, mil-aero and even medical. As well, the complexity of these boards are increasing in the face of stiff competition. This paper discusses the challenges and recently developed design techniques which enable electronics companies to meet aggressive time-to-market goals, lower their development and production costs, and produce more competitive products.

With so many different part numbers running through a production facility, it can be difficult to know how well a process is running. One way that the IC manufacturers solve this issue is to measure specific coupons (test structures) on a parametric die that is placed on each wafer in addition to special parametric wafers. Probe stations can be set up at specific process steps to test these parametric coupons and dies to provide feedback as to whether the process is running in bounds.

Having a specific coupon that is sensitive to a specific process can signal a process problem before it hurts production. The accumulation of these process effects on design can be measured at final test and should correlate with a specific first-pass yield (FPY) model.

The coupon methodology can also be applied to PCB manufacturing. There are many parametric analysis and characterization coupons available for PCBs, forming an important part of a quality assessment process. These process coupons cover reliability, end-product, work-in-process, and process parameter evaluations.