High Density Interconnect (HDI) is being used more often to meet the growing need for more complex designs in smaller form factors. Beyond some of the more obvious electrical effects of using smaller vias, there is also an impact to the power integrity of a board using HDI. This includes different effects of mounted inductances of decoupling capacitors, changes in plane performance due to reduction in perforation from chip pinouts, and the inherent plane-capacitance changes from using dielectrics of various thicknesses. This paper will examine and quantify these effects, using numerous design examples, including a large conventional through-hole design board that was reduced using HDI.

For advanced signaling over high-loss channels, designs today are using equalization and several new measurement methods to evaluate the performance of the link. Both simulation and measurement tools support equalization and the new measurement methods, but correlation of results throughout the design flow is unclear. In this paper a high performance equalizing serial data link is measured and the performance is compared to that predicted by simulation. Then, the differences between simulation and measurements are discussed as well as methods to correlate the two.

Mixed RF, analog and digital technology boards are becoming commonplace in many industries including wireless telecom, consumer, automotive, mil-aero and even medical. As well, the complexity of these boards are increasing in the face of stiff competition. This paper discusses the challenges and recently developed design techniques which enable electronics companies to meet aggressive time-to-market goals, lower their development and production costs, and produce more competitive products.

With so many different part numbers running through a production facility, it can be difficult to know how well a process is running. One way that the IC manufacturers solve this issue is to measure specific coupons (test structures) on a parametric die that is placed on each wafer in addition to special parametric wafers. Probe stations can be set up at specific process steps to test these parametric coupons and dies to provide feedback as to whether the process is running in bounds.

Having a specific coupon that is sensitive to a specific process can signal a process problem before it hurts production. The accumulation of these process effects on design can be measured at final test and should correlate with a specific first-pass yield (FPY) model.

The coupon methodology can also be applied to PCB manufacturing. There are many parametric analysis and characterization coupons available for PCBs, forming an important part of a quality assessment process. These process coupons cover reliability, end-product, work-in-process, and process parameter evaluations.

Any design project that leverages Field Programmable Gate Arrays (FPGAs) to implement system designs has the opportunity to:

• Reduce total design cycle time by as much as 50%
• Minimize PCB manufacturing costs
• Optimize product profit margin

Early adopters of PCB Optimization technology have validated the concept that FPGA package flexibility can deliver substantial business benefits.

This white paper documents the impact of decisions made during the design of the FPGA-PCB interface, from the assignment of the PCB signal to the FPGA package pins through their effect on product profit margin.

Today's designs have become extremely complex and intricate, creating a need for software tools that support automation, maintain accuracy, and meet short design cycles.

Re-using previously designed circuitry has long been an option for resolving these challenges, but never one that was easy to implement. Software providers have made attempts at providing this capability, but they haven't always caught on. With new, more efficient options at hand, will customers see the value? Will they give it a try? Read about a methodology that can handle today's data-filled design content and still produce proper, reusable designs.