PCB White Papers
Analyzing Crosstalk's Impact on BER Performance: Methods and Solutions
This paper discusses two major issues associated with channel crosstalk that have not been fully addressed previously: models from measurements and algorithms for BER prediction. It presents a practical solution that allows designers to add in “near-end” or “far-end” crosstalk characterized by a group of 4-port S-parameters, rather than to perform multiport parameter characterization. The paper then presents in details two simulation approaches for channel crosstalk: synchronous and asynchronous algorithms, and considers their implementations in time and statistical domains. Finally, it gives examples of the proposed procedures implemented together with IBIS-AMI buffer models and discusses their comparative advantages and limitations.
Improving Characterization of Serial Links by Dynamic Deconvolution from PRBS Responses
Predicting and understanding the performance and the limiting factors of a serial data link is critical to high speed serial design process. To this end we concerned ourselves with characterization of active and non-linear components of serial data links, such as transmitters or buffers, by deconvolution of the impulse response from a pattern in either simulation or measurement environments. Mathematical derivation of the calculation is given for ‘symmetrical’ and ‘asymmetrical’ edges, with discussion of singularity. The practical impact on simulation and measurement methodology is discussed, as well as overall improvement in accuracy with real DUTs. Simulation and measurement results are compared.
Predicting BER to Low Probabilities: Validating of a New Analysis Methodology
This paper has detailed a methodology illustrating how IBIS AMI models can be used in combination with Mentor’s analysis tools to attain very low BER level’s with a high level of confidence with relatively short analysis times. This new approach condenses the simulation time necessary to exhaust weakness that may be present within a HS SERDES link by orders of magnitude. The illustrated method periodically and systemically extracts and analyses the systems dynamic response to ever changing bit sequences to determine the next input pattern that will maximally “stress” the resulting eye. In of itself this process would result in pessimistic results that would generally be much worse than one would observe in hardware. This paper continued to the next step illustrating a method to associate the probability of a given worse case pattern with the results of that pattern allowing one to properly scale the resulting BER plot based on “real” and “valid” simulation events that were discovered by this “active” and “interrogative” method. This in contrast to other methods that attempt to extrapolate from what has simulate to that which has not been simulated merely based on an assumed distribution. Our approach has been validated against experimental data acquired using advanced transceivers designed and calibrated by TI. In addition to validating the method to predict a channels BER to low probability the excellent correlation between the results received by simulation and experimental data validates two other important aspects of the analysis flow: firstly it establishes the accuracy of TI’s IBIS AMI models and secondly Mentor’s ability to accurately generate time domain impulse responses from complex channels that can be used in conjunction with IBIS AMI models to accurately evaluate a links performance. The ability to quickly and accuracy predict a channels BER (to a low level) before a physical prototype exists unlocks the possibility for systems designers to perform solution space analysis ensuring that the design tradeoffs used during analysis will yield systems that perform at the target BER.
Fundamentals of Signal Integrity Analysis
New to Signal Integrity analysis, or just need to brush up on the fundamentals? If so, this white paper is aimed at you. This white paper starts at the very basic, actually before the fundamentals, answering the question “What do I need to know?” The paper begins by identifying and analyzing critical nets. Next, it discusses transmission lines and the problems that arise from the high-frequency noise generated by rapid edge-rate signals. Finally, impedance is reviewed and discussed in the context of impedance and signal integrity.
Plane Noise Effects
High speed digital drivers need a good source of power to produce clean, fast signals. For a driver to switch the state of a signal in tens or hundreds of picoseconds, the power plane must be able to supply significant current over a wide bandwidth. The surge in current creates voltage fluctuations in the power distribution network (PDN) that appear as noise at the power pins of the drivers. This plane noise is then transferred through the driver to the signal that is being driven onto a transmission line. Power integrity analysis tools can provide an impedance profile of the PDN in the frequency domain, and a noise profile of the PDN in the time domain, but it is also useful to see the effect that the noise at the power pin of an IC has on the resulting output signal quality. By extracting a model of the power plane, a simulation can be run using SPICE models for drivers and receivers, revealing the PDN noise effects on the transmitted signal.
Power Integrity in Systems Design: Part 1
This paper discusses the fundamental requirements of power integrity (PI), and the most important concept used in PI, the network impedance. It answers the questions commonly asked by digital designers on how a power delivery network (PDN) is represented, how PDN impedance is generally defined, what the target impedance is and its effective range, and the factors affecting impedance analysis. The paper also addresses the contributions of IC current, package inductance, and on-die capacitance to PDN impedance analysis.
Fast, Robust S-parameter Modeling in HyperLynx GHz
The HyperLynx product suite from Mentor Graphics leads the market in mainstream signal integrity tools because of its intuitive and easy to use interface combined with its accurate and robust simulation technology. The HyperLynx GHz package contains numerous capabilities for high speed memory and multi-Gbit/sec serial channel analysis. This includes the comprehensive and robust support for scattering parameter (S-parameter) model generation, validation and simulation.
Accurate, Multi-GBPS Serial Channel Design Solutions for the Entire Design Team
This document describes of the advantages of deploying HyperLynx to meet the increasingly complex challenges of high speed channel design. An overview is provided of the advanced analysis technology. Finally two case studies are presented exploring the sensitivity of channel design to two design trade-offs: via back-drilling and trace length imbalance.
The design of high performance multi-Gbps channels inevitably requires facing new challenges. One possible approach is to attempt to blindly apply conservative layout guidelines that have been established by the success of previous designs or have been provided in the form of reference designs from an IC vendor. This methodology has merit, but will tend to result in designs that have mediocre performance and require unnecessarily expensive PCB materials and manufacturing processes and/or over-constrain the layout engineer placing components and routing the PCB. An alternative approach that will reduce cost and allow maximum performance is to develop knowledge of how physical design rules affect electrical performance so that appropriate tradeoffs can be applied.
HyperLynx GHz provides an intuitive but powerful suite of tools that allows every member of the high speed serial channel design team to participate in creating the highest quality design while minimizing manufacturing costs. HyperLynx GHz also provides the post layout analysis tools that allow the team to ensure design goals have been met and that the product will operate reliably under field conditions.
Opening Eyes on Fiber Weave and CAF
The signal channels that link high speed processors to memory and various other peripherals, are limited by the inherent characteristics of the printed circuit board. These are what ultimately connect information to the outside world. One limiting factor is the effect of nonuniformity of the glass fiber distribution in the printed circuit substrate material, also known as fiber weave effect (FWE). FWE introduces signal skew and timing errors which place an upper limit on bit rate and trace length.
Establishing Confidence in PDN Simulation
A powerful signal integrity analysis tool must be flexible, easy to use and integrated into an existing EDA framework and design flow. In addition, it is important for the tool to be accurate enough. This report reviews a validation study for the Mentor Graphics HyperLynx 8.0 PI tool to establish confidence in using it for power integrity analysis.
Measuring the Performance of Equalized Serial Data Links Across the Design Flow
For advanced signaling over high-loss channels, designs today are using equalization and several new measurement methods to evaluate the performance of the link. Both simulation and measurement tools support equalization and the new measurement methods, but correlation of results throughout the design flow is unclear. In this paper a high performance equalizing serial data link is measured and the performance is compared to that predicted by simulation. Then, the differences between simulation and measurements are discussed as well as methods to correlate the two.