High Speed Rule Definition and Execution using Mentor's EXPEDITION Flow

Overview

Increasing bus speeds, faster switching speeds, and clock speeds that continue to increase at 40% a year are all causes of high-speed design problems-and hence causes of concern to you, the PCB designer.

Modern printed circuit boards pose two critical problems for hardware engineers and PCB designers:

1. A growing volume of high-speed interconnects as a percentage of the total system.
2. Exponentially increasing design complexity associated with new bus and interconnect technologies like DDR, DDR2, PCI Express, HyperTransport, SATA, etc.

While advances in these interconnect technologies enable higher performance and increased system bandwidth, these gains come at a design cost. Almost without exception, they carry additional educational requirements and design techniques.

This session will discuss how effective high-speed software solutions must handle increasingly complex boards, as well as the increasing number of constraints that are required to ensure that boards work right the first time.

Through the use of real-world examples, a design constraint will be carried through the design process, from initial concept (design topology and driver exploration), through physical adherence (constraint-driven routing), and final full-board verification. The presentation and demo will be based on constraint management, routing, and verification solutions within the Expedition Enterprise design flow.

Time: 10:00 AM - 1:00 PM PST

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Who Should Attend

What You Will Learn