HyperLynx Xilinx Hands On Workshop
Overview
Trilogic, Mentor Graphics, Avnet, and Xilinx cordially invite you to attend a FREE “Hands On Workshop” focused on Signal Integrity Analysis using HyperLynx simulation of Xilinx's interconnect technologies.
This is a technology focused workshop that provides attendance with education and practical experience.
A FREE lunch will be provided during the event. Seating is limited, so register now to reserve your space. We will send you an email to confirm your registration and attendance and provide directions.
Who Should Attend
- Engineers and managers involved in high-speed system design -- particularly in rapid prototyping environments where return on tool investment is critical
- Anyone concerned about high-speed design -- even if you're not a signal integrity expert
- Current HyperLynx customers who want to learn about our newest release, v7.7
- Design and Verification Engineers
What You Will Learn
We will begin with an update of the Xilinx FPGA families including an overview of the Virtex and Spartan-3A Families. A presentation will also be given on the Design Kits available from Mentor and Xilinx.
Session one of the Hands On Workshop begins with a review of basic signal integrity analysis using HyperLynx simulations of interconnect technologies. It continues with a discussion of the effects of increasing clock and data rates, and faster component edge rates on designs.
Session two continues with a discussion of high speed MHz and GHz interconnect simulation, and comparison of synchronous vs. asynchronous design technologies. As an example we will work with Virtex interconnects using IBIS model based simulation techniques.
In session three we will focus on multi-gigabit design issues such as enhanced via modeling, connector modeling, lossy transmission line analysis, multi-bit stimulus, and the use of eye diagrams and eye masks. For this example we will work with Spice model based simulation using Virtex-2 and Virtex-5.