Optimizing FPGA / PCB Integration to Maximize System Performance

Click here to request an event in a location near you.

Overview

As FPGA density and I/O pin counts continue to increase, it becomes imperative for FPGA, System, and PCB designers to work together. Only as a team, can design time and production costs be minimized and maximum system performance achieved.

No longer can companies focus solely on FPGA design goals while disregarding the issues that pin assignments create for PCB routing and performance. Conversely, companies cannot focus solely on PCB layout, as layouts that over-constrain the FPGA will create problems for FPGA place-and-route tools, making it difficult to achieve timing closure.

With I/O Designer, engineers from multiple disciplines can collaborate in a common environment to create FPGA pin assignments optimized for the entire system.This seminar will include an introductory presentation on the theory of FPGA/PCB integration followed by a demonstration of I/O Designer in a PCB design flow.

Time: 10:00 AM - 1:00 PM

Who Should Attend

  • Engineers, Designers, and CAD Managers who are looking for a tool to ease the effort of integrating the FPGA on the PCB
  • Project Managers who are concerned with meeting time-to-market goals while reducing or maintaining design cycle times
  • Anyone currently using, or contemplating using, large FPGAs

What You Will Learn

  • The concepts behind simultaneous optimization of pin assignments for the FPGA and PCB
  • Tips and techniques for improving productivity and system performance
  • Methods for easing the effort of integrating the FPGA on the PCB
© Mentor Graphics Corp. All rights reserved.