Proactive High-Speed PCB Stackup Planning On Demand Webcast

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Overview

As design frequencies continue to increase, it's important to invest time early in the design cycle for stackup planning to ensure your critical nets have the correct impedance. This 1-hour webcast will introduce a design process which will help you plan your stackup to meet the critical electrical parameters of your design. We'll investigate impedance planning for single-ended and differential traces, discussing both analytical solutions and 2D field solutions. Using the HyperLynx Stackup Editor, we'll show how trade-offs can be made between trace width, spacing, and dielectric height to find the right stackup solution for your design while keeping in mind cost and manufacturability.

Who Should Attend

Hardware Engineers, Board Engineers, Design Managers, and Signal Integrity Engineers who:

  • Are interested in the stackup design process
  • Want to learn more about PCB manufacturing
  • Need impedance control for critical nets

What You Will Learn


  • Learn how to effectively design a stackup to meet your signal integrity and manufacturing needs
  • Determine dielectric heights and trace spacing to meet impedance requirements for single-ended and differential signaling
  • Determine adequate trace widths to minimize skin effect losses
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