Signal Integrity Analysis for SERDES Designs Web Seminar: Session II
Overview
Mentor Graphics cordially invites you to attend a webinar to learn how HyperLynx can enable you to quickly and easily perform signal integrity (SI) analysis on SERDES designs. You don't have to be a signal integrity expert or spend weeks in the lab to get results!
Serial interconnects offer multi-gigabit throughput while reducing board real estate. As a result, serial interconnects are making their way into thousands of new designs. Topics covered in this webinar include loss analysis, the effects of vias on serial interfaces, s-parameter modeling, and loss mitigation through the use of pre-emphasis and equalization. We will also discuss how HyperLynx Fast Eye technology generates exhaustive eye diagrams orders of magnitude faster than traditional time-domain analysis
See for yourself why HyperLynx is considered the industry standard for quick, accurate, easy-to-use signal integrity analysis tools.
Time: 2:00 pm - 3:15 pm PST
Who Should Attend
- Engineers and managers involved in design of SERDES interfaces such as PCI Express, SATA etc.
- Current HyperLynx customers who would like to learn how HyperLynx can be used for SERDES designs
- Engineers and managers involved in high-speed system design -- particularly in rapid prototyping environments where return on tool investment is critical
What You Will Learn
We'll show you how to get your boards done quickly and correctly, even if you don't have the time to learn overly-complex signal integrity software tools. In this seminar, you'll learn about:
- Multi-bit stimulus, jitter, and eye diagrams
- Simultaneous simulation with SPICE, s-parameter and IBIS models
- Lossy lines, and frequency-dependent via modeling
- How Fast Eye generates exhaustive eye diagrams orders of magnitude faster than traditional time-domain analysis