Altera's Stratix II GX

Implementing a High Speed Serial Channel with Altera’s Stratix II GX
 
Designing a high speed serial interface with today's FPGAs is becoming a challenge, as a result of increasing device complexity.  While significantly more powerful, the extensive array of design options for optimizing SERDES channels can be daunting.  Altera’s Stratix II GX has over 30,000 possible settings between drive strength, termination, and pre-emphasis settings.  Determining the appropriate settings for your channel can be overwhelming, but Altera and Mentor Graphics have teamed up to provide designers with an innovative solution to reduce the time it takes with a design kit that includes easy model setup and a tool to help you choose your pre-emphasis and equalization settings based on the frequency response of your channel. 

Altera Stratix II GX Design Kit for HyperLynx
 
The Stratix II GX design kit for HyperLynx includes a customized GUI for setting up pre-emphasis and equalization that takes the manual work out of setting up SPICE models for simulation.  Mentor’s Model Configurator allows you to easily adjust driver and receiver settings to optimize channel performance, with an integrated interface to Altera's Pre-emphasis Equalization Link Estimator (PELE) tool.  PELE reads in an S-parameter model of your channel, which can be generated from HyperLynx, and returns estimated optimal settings for the Stratix II GX in the Model Configurator for simulation.  This integrated functionality will significantly reduce the time that is required to choose optimal settings for the Stratix II GX, reducing design cycle time while improving design reliability. 

Important Links for the Stratix II GX™ Design Kit for HyperLynx

• Online Event: Altera Stratix II GX Design Kit for HyperLynx with PELE Support
• Request the Stratix II GX™ Design Kit for HyperLynx
• Request support or additional information on the Stratix II GX™ Design Kit for HyperLynx
• More information about HyperLynx software

Altera Stratix II GX™ Design Kit Details

The Stratix GX™ Design Kit includes Eldo encrypted SPICE models for the Stratix II GX™ HSSI transceivers with pre-built design examples of a chip-to-chip design and a backplane design in the HyperLynx LineSim Free-form Schematic Editor (FFS). The default configuration for each of these is as follows:

In LineSim, you can easily edit and customize these topologies to adjust trace geometry, routing length, as well as adjust pre-emphasis and equalization settings for the Stratix II GX™, or use Altera’s PELE-recommended transceiver settings from the Model Configurator.

HyperLynx makes SPICE Simulation Easier than Ever
The models of the active Stratix II GX HSSI circuitry are transistor-level silicon models that have been correlated by Altera to match the actual silicon design. This ensures that your system implementation is designed with the most advanced and accurate models available. Add to that fully coupled frequency-dependent lossy lines, and advanced via modeling, and you're ready to carefully characterize the signal integrity and degradation issues that are inherent in multi-gigabit design.

Using off-the-shelf SPICE models for signal-integrity simulation can be a daunting task for most hardware engineers. Interconnect simulations are better performed in an environment like HyperLynx that's been built from the ground up for this purpose.