Xilinx Virtex II Pro RocketIO™ Design Kit for ICX

Implement RocketIO multi-gigabit serial transceivers for Xilinx's Virtex-II Pro as part of the serial, multi-gigabit trend, Xilinx Virtex-II Pro™ FPGAs with high-speed RocketIO™ serial transceivers are finding their way into hundreds of new applications. In an effort to make multi-gigabit interconnect implementation as painless as possible, Xilinx and Mentor Graphics have teamed up to provide the RocketIO™ Design Kit for ICX. Pre-configured circuits in this design kit will be ready to simulate for PCB backplanes, minimizing user set up, and allowing you to simulate your designs in just minutes. Use either HSPICE encrypted models with your copy of HSPICE, or use the ICX-SPICE models with the powerful SPICE built into ICX.

Important Links for the RocketIO Design Kit for ICX

• Download the Xilinx portion of the RocketIO Kit for ICX (Device: Virtex-II Pro RocketIO MGT - Download: eldo_v2p_mgt.zip)
• Download the Mentor portion of the RocketIO Design Kit for ICX
• View ICX Product Page
• Click here to Request support or additional information on the RocketIO Design Kit for ICX

Press Release: Mentor Graphics and Xilinx Collaboration Reduces Design Time and Optimizes Performance for Integrated FPGA-on-Board Designs

Xilinx Signal Integrity Simulation (SIS) Kit Details
The Xilinx SIS kit, and the associated RocketIO models are required in conjunction with the RocketIO for ICX Design Kit. The SIS Kit includes a backplane topology that can be used as is, or edited in ICX.

The default configuration for each of these is as follows: transmitter driver - package - 2" long FR4 trace - HSD5 AB pair connector - 16" long FR4 trace - HSD5 AB pair connector - 2" long FR4 trace - package - receiver buffer. The FR4 traces used are a differential pair of centered striplines, which are 12 mils wide and 20 mils apart, with a Z0O (odd mode characteristic impedance) of 50.

RocketIO Design Kit for ICX Contents
The RocketIO for ICX Design Kit will install over the top of the Xilinx SIS Kit, and include a full implementation of each of the SIS Kit examples, along with a RocketIO for ICX User Guide.

The figure below shows ICX simulation results for the Backplane example, which conforms to a XAUI backplane. The backplane example includes a transmitter driver on one chip to a receiver buffer on a different chip through FR4 traces and a Teradyne VHDM-HSD5 connector.

RocketIO XAUI backplane example in ICX

Powerful, Encrypted HSPICE Support in ICX Using off-the-shelf SPICE for signal-integrity simulation is a daunting task for most hardware engineers. Interconnect simulations are better performed in an environment like ICX that's been built from the ground up for this purpose, and includes support for IBIS BIRD 75, enabling complete package pinouts within the IBIS framework-even for an encrypted HSPICE model. ICX gives you the best of both worlds: rigorous transistor models, with the unmatched power of ICX.

ICX is compatible with PCB layout systems from:

Mentor Graphics Expedition™ and Board Station™
Cadence Allegro