The new technology, available around the end of 2006 with Mentor's Expedition and Board Station design flows, has two applications. The first is a topology planner used by engineers to plan and optimize bus systems and subsystem interconnects. The second is a topology router that enables the board designer to automatically route the bus connections.

Over the past 30 years, said John Issac, director of marketing development at Mentor Graphics, developers have tried to make autorouters think like designers. That's been difficult, he said, because autorouters look at one route at a time, while designers recognize larger patterns like bus connections between components.

"This is the first time . . . we have written algorithms that combine the skill of a designer with the speed of autorouting," Isaac said. What Mentor is offering, he said, is the first "topology router" that enables users to plan bus topologies and then automatically route the connections.

Isaac said demand for this capability comes largely from consumer electronics, where saving a pc board layer can make the difference between a profitable and unprofitable product. A major Japanese computer supplier that asked not to be named, he said, helped define requirements and was a beta tester for the topology router.

Isaac said the topology router can handle any kind of bus, including parallel-bus structures and differential-pair structures for serdes or serial interconnects. In the future, he said, Mentor will extend the technology to clock networks and other "structures that are typically predefined and need special guidance."

The topology-planning phase is interactive. When it begins, the schematic is typically predetermined and the number of nets predefined. Engineers graphically define a bus structure for the pc board, select the number of bits and view direct connections between pins. Engineers can determine the width and shielding a bus needs.

Bus structures can include splits, branching, layer changes and connection points to many components. Each bus contains information about signals, clearances and branch points, and the routing layer and topology rules the autorouter must obey. The plan thus helps assure that buses will meet delay requirements without requiring rerouting.

During planning, engineers can add special routing controls, like trace shielding and via fanout preferences. For example, the plan can shield every fourth bit with ground. Engineers can also specify "high-speed tuning areas," or locations along the bus path that can be tuned to optimize delay. Here, for example, the router might introduce trombone interconnects.

Because the topology plan is part of the layout database, engineering change orders (ECOs) are easy, Isaac said. "I may have routed all my buses, and now an ECO comes down," he said. "Because the path constraints are all stored in one database, it's a small incremental change as opposed to redoing the whole bus structure."

When the bus topology passes to the board designer, the topology router is fully automatic, Isaac said. There will probably be some iterations on the routing before it's finalized, he said, so designers may need to go in and clean up the ends of the routes. "The autorouter might not route to the highest quality a designer could achieve at the ends of these bus structures," Isaac said. "It will provide 99 percent of the bus structure but you might have to add an additional 1 percent at the end."

Mentor's topology router is in controlled release today, with a general release later this year or early 2007. It will be an option to either Expedition or Board Station. Pricing has not yet been determined.

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