Technical Publications
IBIS Modeling of LVDS Buffers
This report provides detailed information on a study of the effects of internal series termination between positive and negative I/O pads in LVDS buffers. Comparisons between IBIS and SPICE simulations are used to emphasize these effects. Different loading conditions and modeling approaches are considered. IBIS modeling approaches for LVDS buffers are presented. Model validation shows the power of these approaches over other conventional techniques.
Simultaneous Design Technology: A Revolution
New software technology has been developed that enables effective parallel design of a circuit board. This technology enables multiple designers, processes and heterogeneous tools to work on the same design database simultaneously and achieve significant gains in design productivity. But, unlike classical divide - and conquer methods that break down a design into pieces and operate on them independently, this new technology enables concurrent progress on a common database, automatically synchronizing changes and resolving conflicts - a first in the EDA industry. This paper focuses on the methods and applications of new parallel design technology that offers a novel paradigm for circuit board design. Topics include:
- Review of design problems and concurrent methods
- Parallel design architecture
Applying the parallel design technology to:
- Layout
- Autorouting
- Circuit and Board Design
- System Design
Unbalanced Tracks and Differential Impedance
"The calculation of the differential impedance of unbalanced tracks is more complicated…because geometrical and electrical symmetry cannot be used."
This paper discusses the effect of track unbalance on the differential impedance value and provides a method for calculating that value. Differential impedance was determined from the capacitance and inductance matrices of the unbalanced tracks, and the results for both edge-coupled microstrip and stripline are given. Several tables and graphs illustrate the variations.
Differential Trace Design Rules: Truth vs Fiction
There is no shortage of design rules available when people talk about differential traces on circuit boards. At various times you can hear people argue that there is a need for, or there is no need for, a variety of special rules regarding continuity of ground planes underneath the traces, equal length traces, equal separation between traces, differential impedance control, etc. So let's set the record straight. NONE of these rules are inherently required by the fact that we are using differential signals! But some of them might be required if we are worried about signal integrity issues in our designs. This article looks at these individual types of rules from the standpoint of various signal integrity issues to see when, if ever, they need be applied.
Transmission Line Terminations
Termination strategies are effective in eliminating, or at least controlling, transmission line reflections. There are five types of termination strategies commonly used with transmission lines (parallel, AC, Thevenin, Series, and Diode.) This paper looks at each strategy and summarizes its strengths and weaknesses. In addition, simulations are illustrated for two of tem (AC and Series), helping to illustrate their unique characteristics.
Pad Capacitance Extraction for IBIS Models
"Higher frequencies, lower voltage swings and faster rise/fall times are strongly required for today's applications."
Pad capacitance has an important effect on IBIS (Input/Output Information Specification) behavior models used in signal integrity simulation. This paper presents a new technique for pad capacitance extraction based on detecting the resonance frequency of a tank circuit, resulting in the calculation of the overall seen pad capacitance.
Several input-output buffer technologies are used to verify this technique. Positive validation results are shown by Spice simulation. The additional validation of a transistor with a single capacitance-voltage equation proves the effectiveness of the proposed technique
Microstrip Propagation Times: Slower Than We Think
Most of us have been using incorrect values for the propagation speed of our microstrip traces! The correction factor for Er we have been using all this time is based on an incorrect premise. In particular, it results in a value for propagation speed that is independent of variations in trace width and height above the reference plane. But the propagation speed for microstrip traces depends significantly on such variations. This article explains why and develops a superior model for estimating propagation speeds and propagation delays for microstrip configurations.
Termination Placement in PCB Design
When we use transmission line techniques to control reflections on circuit board traces, we must terminate the lines. Typically we do so with resistors placed at the beginning (series termination) or at the end (parallel or Thevenin termination) of the trace. An interesting question is, "Where do we place these terminating resistors?" The more obvious assumption that we place them" as close as possible" to the end of the trace may not be the best answer. This article looks closely, with the aid of some simulations, at precisely where terminating resistors should be placed, and why.
3.125 Gbps with your Hair on Fire - Simulation-Based Signal-Integrity Analysis of Digital Interconnects at Multi-Gigabit Speeds
As clock frequencies and data rates soar, system designers are being forced to account for the effects of degraded high-frequency signals, causing otherwise healthy signals to be potentially unrecognizable at receiver ICs. This technical paper will focus on simulation-based signal-integrity analysis of multi-gigabit interconnects using Mentor Graphics' HyperLynx{reg} GHz product. Techniques will be presented for using both HSPICE and IBIS buffer models in concurrent simulations; along with eye-diagram and jitter analysis using multi-bit stimuli, while accounting for line loss, inter-symbol interference, and advanced via modeling.
What You Lose From a Lossy Line
Lossy transmission line effects dominate signal integrity at clock frequencies above about 1 GHz and interconnect lengths above about 12 inches. An ideal lossy transmission line model is required to predict the effects of rise time degradation, ISI, collapse of the eye diagram and deterministic jitter. With a flexible simulation tool, design and material selection decisions can be made early in the design process to optimize the balance of cost and performance in high speed digital systems.