Design for Testability

Insufficient attention to test access can cost thousands of dollars in poor production yield. Performing detailed physical testability analysis can determine not only if a printed circuit board meets the users ideal guidelines but also to evaluate the consequences in the areas where the guidelines are not met.

Physical access analysis can be performed early in the design cycle to make sure test is incorporated in to the layout as well as part of the implementation of the test strategy. In the latter case, test probe locations are evaluated and placed before the final machine specific files are generated based on the actual test access.

• Reduce costly PCB layout spins by performing test analysis early
• Graphically collaborate on test issues to reduce time to market
• Mixed vendor machine supports enables all equipment to be supported from one environment

Does soldermask data cause you problems with DFT analysis?

• Is soldermask missing from your CAD data?
• Is it complete?
• Is your current DFT software making assumptions on accessibility of features?

CAMCAD DFT Soldermask Analysis can:

• Use soldermask data from the original CAD
• Import soldermask Gerber layers when the soldermask data is missing from the CAD
• Import soldermask Gerber layers when the soldermask data is incorrect in the CAD
• Merge area and padstack soldermask data together
• Peform true exposed metal analysis of electrical pad area due to soldermask and component violations
• Display the results as an easy to view layer that is superimposed over the board.

Automatic offsets for flying probe test systems

CAMCAD DFT saves considerable time and mistakes by automatically applying offsets to access points on the board. Users can decide to offset surface mount, via and through-hole access markers individually. CAMCAD DFT will then automatically move the access markers away from the body of the component depending on the size of the exposed metal area previously calculated.