Design Kits
Mentor Graphics has teamed up with several vendors to provide the following design kits and reference designs to accompany industry-leading high-speed design and PCB layout tools. These vendor specific designs provide Mentor customers with faster design implementation, increasing time to market and reduced design iterations.
Multi-Gigabit Design Kits
Multi-gigabit design kits enable easy simulation analysis, implementation of multi-gigabit technologies, and allow engineers to quickly get started simulating.
The following capabilities are enabled with the Mentor multi-gigabit design kits, and high speed tools:
- Eye-diagram, jitter and inter-symbol interference analysis
- Multi-bit stimuli
- Lossy line modeling
- Advanced via modeling
- Simulation with encrypted HSPICE or IBIS models
Xilinx Virtex II Pro RocketIO™ Design Kit for HyperLynx
Altera Stratix GX™ Design Kit for HyperLynx
Altera Stratix GX II Design Kit for HyperLynx
PCB Reference Designs
Altera Stratix Reference Design and Footprint for PADS Layout
Xilinx Footprint Library for PADS Layout
Xilinx Virtex-II AFX™ Reference Design for PADS Layout
Why Do I Need a Multi-Gigabit Design Kit?
Electronic hardware design is experiencing a distinct trend toward serialized, asynchronous architectures. In this world, existing bus standards such as PCI and ATA are being replaced with serialized versions like PCI Express and ATA-2. Serialized, multi-gigabit signaling addresses the critical problem of how to push data rates into the multi-Gbps range, where "classic" parallel, synchronous bus techniques become impractical.
Gbps data channels, are serial (hence the need for SERializers and DESerializers), extremely fast, and often travel over interconnects without explicit clocks. Multi-gigabit, serial-or SERDES designs, as they are often called-serializes a parallel data bus into one or more "lanes" or bit streams and embeds the clock information within the data stream.
New Design and Analysis Techniques are needed
This next generation I/O architecture offers the promise of decreased routing density, point-to-point connections, and elimination of clock trees, reducing overall system design complexity. Sophisticated receiver ICs use techniques like equalization to "recover" signals after they're seriously degraded by propagation across a PCB or down a cable. With these system-level benefits, Next Generation serial I/O also requires improved analysis techniques to address these issues, including:
- Improved modeling and analysis of transmission-line loss in PCB interconnects
- Improved modeling of vias and connectors
- Improved modeling and analysis of I/O "internals" to simulate the additional functionality they require, including "pre-emphasis"
It is for these reasons that Mentor Graphics is adding software enhancements that are absolutely critical to multi-gigabit design, as well as design kits that make this easier than ever.