PADS Layout Options

Advanced Packaging Toolkit | Advanced Rule Set | Chip-on-Board | Critical Place & Route | Database Viewer | Design for Test | High Speed Routing | IDF Link | Physical Design Reuse

PADS Layout Options
PADS Layout is a robust design solution for the layout of complex printed circuit boards. Its expansive array of core capabilities address most designs, yet PADS Layout can be enhanced as needed when specialized projects arise.

Add-on modules include:

1. Advanced Packaging Toolkit
   Significantly reduces package design time for PADS Layout users who work with bare-die components such as single- and few-chip modules and chip-on-board. The Advanced Packaging Toolkit includes the Chip-on-Board Toolkit.
   
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2. Advanced Rule Set (ARS)
   Defines and routes component clearance and routing rules interactively or in batch mode. With ARS, you can define rules for min/max length and differential pairs and use batch DRCs to ensure that your high-speed constraints are met. Maintenance customers who owned the earlier EDC and ERS options received an ARS license free of charge.
   
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3. Chip-on-Board (COB) Toolkit
   Scaleable functionality for bare-die design needs. The COB Toolkit includes a die wizard, wire bond wizard, and report generation. Additional functionality is available in the Advanced Packaging Toolkit (see above).
   
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4. Critical Place & Route (CPR)
   Defines, verifies, and enforces essential pre-placement and pre-layout design rules. These essential design rules are easily passed along and maintained, ensuring continuous quality.
   
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5. Database Viewer (PCBview)
   Improves productivity and streamlines departmental communication. With the Database Viewer, everyone from corporate and project managers through purchasing and manufacturing professionals can easily access and view the same data in a timely and effective manner.
   
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6. Design for Test (DFT Audit)
   Provides automated database updates for test-point insertion. Includes test-point preservation features that optimize results by enabling PCB test engineers to evaluate testability based on user-defined strategies. Also includes testpoint autorouting capabilities for optimal testpoint insertion.
   
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7. High Speed Routing
   (PADS Router HSD, PADS AutoRouter HSD)
   Interactive and automatic high-speed routing options are available for PADS Layout. With these options you can: route length-constrained nets, manage high-speed constraints, set and protect net topologies, and much more. NOTE: High-speed routing requires the Advanced Rule Set (see ARS, above).
   
   
8. IDF Link
   Connects PADS Layout to CAD/CAM solutions such as Pro/ENGINEER. With IDF Link, designers can investigate how a placed printed circuit board will be modeled as a subassembly in a larger, or final-product, solids model.
   
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9. Physical Design Reuse (PDR)
   Supports the creation, saving, and placement of physical design reuse elements independent of the schematic source. Allows you to replicate golden circuits in new designs or replicate circuits multiple times within an existing design. With PDR, it is easy to reuse tested, proven circuitry to reduce errors and minimize design time.
   
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