The Tessent® Product Suite
Tessent combines features of deterministic scan testing, embedded pattern compression, built-in self test, specialized embedded memory test and repair, and boundary scan, as well as board and system-level test technologies.
The Tessent product suite provides comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug, and yield ramp for today’s SoCs. Built on the foundation of the best-in-class solutions for each test discipline, Tessent brings them together in a powerful test flow that ensures total chip coverage.
Mentor Graphics offers the industry's most powerful suite of logic test solutions with more than two decade of successful high-quality test on thousands of tape-outs using both compression and vectorless approaches.
The Tessent® silicon learning products increase productivity during critical silicon validation and yield ramp phases, providing solutions for test bring-up, silicon characterization, diagnosis-driven yield analysis, and failure analysis.
Connect with Us
- Tessent Diagnosis Tessent DiagnosisBangalore, IN • http://www.mentor.com/training/courses/tessent-diagnosisJan 23 Tessent DiagnosisSingapore, SG • http://www.mentor.com/training/courses/tessent-diagnosisMar 6
- Tessent IJTAG Tessent IJTAGFremont, CA • http://www.mentor.com/training/courses/tessent-ijtagFeb 18–19 Tessent IJTAGFremont, CA • http://www.mentor.com/training/courses/tessent-ijtagApr 21–22
- ASSET InterTech/Mentor Graphics DFT Technology Seminar ASSET InterTech/Mentor Graphics DFT Technology Seminarhttp://www.mentor.com/events/dft-technology-seminarAustin, TX • Feb 19, 2015 ASSET InterTech/Mentor Graphics DFT Technology Seminarhttp://www.mentor.com/events/dft-technology-seminarSan Diego, CA • Feb 24, 2015 ASSET InterTech/Mentor Graphics DFT Technology Seminarhttp://www.mentor.com/events/dft-technology-seminarIrvine, CA • Feb 25, 2015