The Tessent® Product Suite
Tessent combines features of deterministic scan testing, embedded pattern compression, built-in self test, specialized embedded memory test and repair, and boundary scan, as well as board and system-level test technologies.
The Tessent product suite provides comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug, and yield ramp for today’s SoCs. Built on the foundation of the best-in-class solutions for each test discipline, Tessent brings them together in a powerful test flow that ensures total chip coverage.
Mentor Graphics offers the industry’s most powerful suite of logic test solutions with more than a decade, and thousands of tape-outs, of successful high-quality test using both compression and vectorless approaches.
The Tessent® silicon learning products increase productivity during critical silicon validation and yield ramp phases, providing solutions for test bring-up, silicon characterization, diagnosis-driven yield analysis, and failure analysis.
- Tessent MemoryBIST Tessent MemoryBIST Hsinchu City, TW • http://www.mentor.com/training/courses/tessent-memorybistMar 19–20 Tessent MemoryBIST Online • http://www.mentor.com/training/courses/tessent-memorybistApr 14–16
- Tessent Scan and ATPG Tessent Scan and ATPGHsinchu City, TW • http://www.mentor.com/training/courses/tessent-scan-and-atpgMar 25–26 Tessent Scan and ATPGFremont, CA • http://www.mentor.com/training/courses/tessent-scan-and-atpgApr 22–25