Silicon Test and Yield Analysis

Introducing the Tessent™ Product Suite

Tessent combines features of deterministic scan testing, embedded pattern compression, built-in self test, specialized embedded memory test and repair, and boundary scan, as well as board and system-level test technologies.

The Mentor Graphics Tessent™ product suite provides comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug, and yield ramp for today’s SoCs. Built on the foundation of the best-in-class solutions for each test discipline, Tessent brings them together in a powerful test flow that ensures total chip coverage.View the Tessent Product Suite Datasheet

Tessent TestKompress

This product presentation describes the advantages of using Tessent TestKompress for managing test quality, test time, design flow, and test pattern generation throughput. Basic and advanced fault models... View Product Demo

Tessent LogicBIST

This product presentation describes how, by including test logic on the IC, the need for expensive external test equipment and test patterns can be removed. Tessent LogicBIST uses an approach that provides... View Product Demo

Tessent MemoryBIST

In today’s ICs, memory commonly can take up more than 50% of the available silicon area. There is a growing need to make changes to the test algorithms during manufacturing test, and repairable memories... View Product Demo

STIL Checker

The first commercially available syntax checker and verification tool for the STIL language, enabling developers of ATE, EDA, and related tools to ensure compatibility with STIL-based flows. Download STIL... View Software Evaluation

Test of Time Award Nomination

Tessent™ LogicBIST has been nominated for Test and Measurement World’s Test of Time award for 2009. The process to vote for this award is pretty straight forward. Go to the Ballot.

Silicon Yield Solutions

Logic Test Solutions

The Tessent logic test solutions provide best-in-class ATPG, compression, and logic BIST.

Memory Test Solutions

The Tessent memory BIST solutions provide advanced integration automation, test algorithm programmability, and self-repair.

Mixed-Signal Test

The Tessent mixed-signal test solutions provide complete, parametric, embedded test for PLLs, DLLs, clock signals, and multi-Gb/s SerDes.

Silicon Learning

The Tessent silicon learning solutions provide defect and timing error identification, yield analysis, and interactive debug and characterization.

Technology Overviews

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Comprehensive Solution for Silicon Test and Yield Analysis

Technology Overview

Built on the foundation of the best-in-class test tools for each test discipline, Tessent brings these solutions together in a powerful test platform that ensures total chip coverage. View Video

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Mentor Graphics Vision for Silicon Test and Yield Analysis

Technology Overview

Joe Sawicki, VP of Design to Silicon, talks about the vision for Mentor Graphics silicon test and yield analysis product suite, Tessent. View Video

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