Silicon Test and Yield Analysis
The Tessent® Product Suite
Tessent combines features of deterministic scan testing, embedded pattern compression, built-in self test, specialized embedded memory test and repair, and boundary scan, as well as board and system-level test technologies.
The Tessent product suite provides comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug, and yield ramp for today’s SoCs. Built on the foundation of the best-in-class solutions for each test discipline, Tessent brings them together in a powerful test flow that ensures total chip coverage.
Tessent TestKompress with Cell-Aware Testing
Mentor Graphics
"Cell-aware" automatic test pattern generation is being used to find the defects that occur within cells. Tessent TestKompress automates the analysis of cell libraries with a tool called CellModelGen and a language for creating user-defined fault models. This cell-aware methodology uses the physical characterization of cells to generate test patterns deterministically for potential defect locations.
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Tessent Silicon Test & Yield Analysis Solution
Logic Test
Mentor Graphics offers the industry’s most powerful suite of logic test solutions with more than a decade, and thousands of tape-outs, of successful high-quality test using both compression and vectorless approaches.
Memory Test
Tessent® memory test solutions include comprehensive test and diagnostic capabilities to address the quality requirements of new process nodes and memory designs as well as comprehensive repair analysis and self-repair capabilities.
Mixed-Signal Test
The Tessent® mixed-signal test solutions are vendor- and ATE-independent, addressing the growing number of SerDes interfaces and PLLs on today’s SoC designs.
Silicon Learning
The Tessent® silicon learning products increase productivity during critical silicon validation and yield ramp phases, providing solutions for test bring-up, silicon characterization, diagnosis-driven yield analysis, and failure analysis.
White Papers
Automated Test Creation for Mixed Signal IP using IJTAG
The creation of test patterns for mixed signal IP has been, to a large extent, a manual effort. To improve the process used to test, access, and control embedded IP, the new IEEE P1687 standard 1 is being... View White Paper
Ready for 3D-IC
This technical presentation describes the challenges and Mentor's solutions for verifying and testing IC designs targeted for 3D packages, such as stacked die using TSVs or multi-die packages using silicon... View White Paper
Low Power Test
Today’s advanced integrated circuit (IC) designs are increasing in complexity, with their seemingly endless progression to smaller geometries, ever increasing integration between analog and digital... View White Paper