Silicon Test and Yield Analysis

Introducing the Tessent™ Product Suite

Tessent combines features of deterministic scan testing, embedded pattern compression, built-in self test, specialized embedded memory test and repair, and boundary scan, as well as board and system-level test technologies.

Silicon Test and Yield Analysis Online Presentations

Avago Technologies and Mentor Graphics: Test Challenges and Solutions

Jason Brown, World Wide Test Manager, Avago Technologies, and Jay Jahangiri, Technical Marketing Engineer, Mentor Graphics, speak about silicon test challenges and solutions. View Testimonial

Comprehensive Solution for Silicon Test and Yield Analysis

Built on the foundation of the best-in-class test tools for each test discipline, Tessent brings these solutions together in a powerful test platform that ensures total chip coverage. View Technology Overview

Tessent Silicon Test & Yield Analysis Solution

Comprehensive Solution

The Tessent product suite provides comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug, and yield ramp for today’s SoCs. Built on the foundation of the best-in-class solutions for each test discipline, Tessent brings them together in a powerful test flow that ensures total chip coverage.

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