Silicon Test and Yield Analysis
Introducing the Tessent™ Product Suite
Tessent combines features of deterministic scan testing, embedded pattern compression, built-in self test, specialized embedded memory test and repair, and boundary scan, as well as board and system-level test technologies.
Tessent Silicon Test & Yield Analysis Solution
Comprehensive Solution
The Tessent product suite provides comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug, and yield ramp for today’s SoCs. Built on the foundation of the best-in-class solutions for each test discipline, Tessent brings them together in a powerful test flow that ensures total chip coverage.
Quick Links
A Guide to Power-Aware Memory RepairLearn more about an effective memory repair methodology.
EDA Tech Forum
Event: Free, one-day events are packed with industry expert keynotes and technical sessions presented by design area professionals. Sep 16, 2010 : Santa Clara, CASep 21, 2010 : OnlineOct 14, 2010 : Boston, MA View Event
News & Press
- RICOH Achieves Full Test Coverage with Ultra-Low Pin Count Using Mentor Graphics Tessent TestKompress
- Mentor Graphics Design-to-Silicon Solutions Used in Successful Development of TSMC 28nm Product Qualification Vehicle Test Chip
- Mentor Graphics Tessent YieldInsight and FloEFD Products Selected for EDN Magazine’s Hot 100
- Freescale Semiconductor Collaborates with Mentor Graphics on Tessent Silicon Test, Yield Analysis, Calibre Physical Verification and DFM
- More