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Silicon Test and Yield Analysis Blog

15 Nov, 2014

Testing Your Limits

Posted by Shelly Stalnaker

Shelly Stalnaker Are you a calm person? Or are you easily irritated? We all have our limits and pressure points—just like a design layout. Certain geometries may have a high failure rate in production. Circuitry may fail when confronted with an ESD event. When your design passes verification, does that mean it’s all good? In theory, yes. In reality, everyone knows that the real world is a tough place for electronics. … Read More

7 Sep, 2014

Shelly Stalnaker The 9th annual International Electrostatic Discharge Workshop (IEW) is being held May 4-7, 2015, at the Granlibakken Resort in Lake Tahoe, CA. The Call for Papers promises glimpses of “friendly but shy” bears and other wildlife at the conference site, located at 6,350 feet up in a mountain valley. Frankly, I prefer my bears to be decidedly shy, if that means they’ll be close enough … Read More

28 Aug, 2014

It's Electrifying!

Posted by Shelly Stalnaker

Shelly Stalnaker I have one opinion about electricity…if it’s invisible and it can kill you, it’s probably a good idea to avoid it. Now, some of my attitude is shaped by spending most of my childhood along the US Gulf Coast, where massive thunderstorms are an almost-daily occurrence during summer, and every little kid is taught to run for cover at the first rumble or flash. But that healthy fear means … Read More

25 Aug, 2014

Shelly Stalnaker Are you stressed out over the effects of stress in your IC designs? Relaaaax…help is here! A new publication on mechanical stress in ICs, co-edited by Valeriy Sukharev, Principal Engineer for Calibre R&D, has just been released by AIP Publishing. Stress-Induced Phenomena and Reliability in 3D Microelectronics includes papers from international workshops held in the U.S., Germany, and Japan. … Read More

18 Aug, 2014

Testing the Boundaries of Good Design

Posted by Shelly Stalnaker

Shelly Stalnaker In a SPIE.TV interview, Joseph Sawicki, Vice-President and General Manager of the Design to Silicon division of Mentor Graphics, explains the challenges of moving from design abstraction to physical implementation to a successful yield. “Design to silicon” is a complex process that continuously blends evolutionary trends, such as enhancements to 3D mask design and yield learning, with more … Read More

14 Aug, 2014

Shelly Stalnaker Design-style-based (systematic) defects are the major challenge to yield ramp at advanced process nodes, adding to the complexity of the basic process ramp. Because of its involvement in the design, manufacturing, and test, EDA is in a unique position to contribute toward the control, if not the solution, of this problem, through the use of automated pattern detection and analysis. Patterns can be useful … Read More

7 Aug, 2014

Failing to Succeed

Posted by Shelly Stalnaker

Shelly Stalnaker Failure analysis is a critical process in successful IC production. No matter how comprehensive the design rules are, no matter how thorough the verification strategies are, there will be chip failures in production. Understanding the cause of these failures is crucial to being able to implement design strategies and corrective technology to ensure the failures are eliminated in future designs. At its … Read More

22 Jul, 2014

Global Warming

Posted by Shelly Stalnaker

Shelly Stalnaker If you’re designing large die such as a system-on-chip (SoC) with high power demands, you’d better be thinking about how to get the heat out. Poor heat dissipation can lead to a sub-optimal packaging solution from cost, size, weight and performance perspectives. Historically, designers assumed the die temperature was uniform. Not any more. Heating due to current leakage makes power dissipation … Read More

21 Jul, 2014

Won't You Please, Please Help Me?

Posted by Shelly Stalnaker

Shelly Stalnaker No, that’s not really a cry for help, at least not from me. But I can imagine a lot of designers saying just that as they try to understand and implement multi-patterning requirements. LELE? LELELE? LELELELE? SADP? SADP SIT? Whhaaaatttt???!!! And help we have. In spades. Our resident multi-patterning expert, David Abercrombie, not only writes extensively about multi-patterning issues, but he is … Read More

20 Mar, 2014

3D Yoga

Posted by Shelly Stalnaker

Shelly Stalnaker

I practice yoga because it helps with my flexibility. Of course, that’s a little like saying that lighting a candle helps with heating your house, but I digress. The point is, flexibility is generally a good thing, and that holds true for 3D ICs and their test strategies. As discussed in the Electrical Engineering Journal, a flexible 3D test strategy that uses a “plug-and-play” architecture

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Silicon Test, Etienne Racine, IC test, 3DIC, Martin Keim, Ron Press, IEEE P1687, IJTAG

17 Mar, 2014

Little Orphan Annie

Posted by Shelly Stalnaker

Shelly Stalnaker

Is design-for-test the forgotten stepchild of IC design? Not any more, and DFT engineers can, in large part, thank the automotive industry. The number of processors built into a vehicle is steadily increasing, as we all know (okay, maybe not that guy driving the 1969 Chevy Camaro). These chips have to meet very high standards for quality and reliability, which means the companies who make them need

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automotive test, Silicon Test, Cell-Aware ATPG, cell-aware, ATPG, logic BIST, Cell Aware Test, Ron Press, embedded compression, semiconductor test, iso26262

18 Feb, 2014

Esperanto for ICs

Posted by Shelly Stalnaker

Shelly Stalnaker In Standards & Travels on EE Times, Bruce Swanson reminisces about a trip he took to Europe, long before there were cell phones, a common currency, or even the Internet. Dealing with different languages, different currencies, and different local customs took time, was a bit frustrating, and sometimes led to mistakes (WHERE is this train going?!). His experiences on that trip came to mind recently … Read More

IEEE standard, IJTAG, desgin for test, yield analysis, P1687, Silicon Test

13 Feb, 2014

Is your car safe to drive? Are you sure?

Posted by Shelly Stalnaker

Shelly Stalnaker The number of electronic devices used in vehicles is increasing exponentially, for everything from braking to engine control to navigation to collision avoidance. Devices used in safety-critical applications like these not only require very high quality testing at the time of manufacture, but also built-in self-test capability, so they can be tested within the safety-critical application. Advanced design-for-test … Read More

16 Jan, 2014

Can You Benefit from Cell-Aware Test?

Posted by Shelly Stalnaker

Shelly Stalnaker With the move to small geometries, existing fault models such as stuck-at, transition, bridging, open, and small-delay are becoming less effective at ensuring desired quality levels. While these models only consider faults on cell inputs/outputs and interconnect lines between cells, more defects increasingly occur within the cell structures. A new cell-aware test that directly targets specific shorts, … Read More

test pattern, Tessent, defect detection, ATPG, IC, scan test, fault models, FinFET

14 Jan, 2014

Are you the 1%?

Posted by Shelly Stalnaker

Shelly Stalnaker Do you have a product that has been manufactured for quite some time at a high volume? If so, maybe it makes financial sense to chase down that last 1% of yield loss. In Geir Eide’s article on EDN.com, he explains how diagnosis-driven yield analysis (DDYA) can help you quickly and efficiently identify the root cause of yield loss, and separate design-based from process-based yield loss. Still … Read More

yield loss, diagnosis-drive yield analysis, Foundry, DDYA, root cause analysis, root cause deconvolution, layout-aware can diagnosis, RCD

 
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