In Standards & Travels on EE Times, Bruce Swanson reminisces about a trip he took to Europe, long before there were cell phones, a common currency, or even the Internet. Dealing with different languages, different currencies, and different local customs took time, was a bit frustrating, and sometimes led to mistakes (WHERE is this train going?!). His experiences on that trip came to mind recently … Read More
Silicon Test and Yield Analysis Blog
Are you a TSMC customer or partner? If so, you’ll want to take a look at our presentations from the 2013 TSMC Open Innovation Platform conference. Design Reliability with Calibre YieldEnhancer/SmartFill and Calibre PERC Broadcom & Mentor Graphics The complexity of advanced technologies drives new requirements for poly/OD and metal fill to solve critical manufacturing effects, and more importantly … Read More
The number of electronic devices used in vehicles is increasing exponentially, for everything from braking to engine control to navigation to collision avoidance. Devices used in safety-critical applications like these not only require very high quality testing at the time of manufacture, but also built-in self-test capability, so they can be tested within the safety-critical application. Advanced design-for-test … Read More
With the move to small geometries, existing fault models such as stuck-at, transition, bridging, open, and small-delay are becoming less effective at ensuring desired quality levels. While these models only consider faults on cell inputs/outputs and interconnect lines between cells, more defects increasingly occur within the cell structures. A new cell-aware test that directly targets specific shorts, … Read More
Do you have a product that has been manufactured for quite some time at a high volume? If so, maybe it makes financial sense to chase down that last 1% of yield loss. In Geir Eide’s article on EDN.com, he explains how diagnosis-driven yield analysis (DDYA) can help you quickly and efficiently identify the root cause of yield loss, and separate design-based from process-based yield loss. Still … Read More
If you’re designing low power, high performance ICs, you need to understand the design, verification, and test requirements that these products require. Elements like accurate, efficient hierarchical power grid analysis, leakage optimization, electromigration analysis, and BIST strategies for low-power designs. Learn about all of these, and more, in the Power-Aware A-Z blog at Semiconductor Engineering. … Read More
Technical Article 3D-stacked designs containing a mix of separate logic and memory die represent a somewhat new application for memory BIST (built-in self-test), compared to the more conventional single-die embedded SRAM implementations. Gaining access to a DRAM requires predefined customized memory operations that provide a cost-effective solution for testing 3D ICs. EDA tools must make this definition … Read More
The creation of test patterns for mixed signal IP has been, to a large extent, a manual effort. The new IEEE P1687 standard, also called IJTAG, simplifies the access, control and testing of embedded IP, and is expected to be rapidly and widely adopted by the semiconductor industry. Mentor Graphics and NXP Semiconductors (NXP) worked together to implement P1687 on mixed-signal IPs in a 65 nm automotive … Read More
Integration and testing of IP blocks in large SOCs has been a manual, time consuming design effort. A new standard called IEEE P1687 (or "IJTAG") for IP plug-and-play integration was created to simplify these tasks and EDA tools are emerging to support the standard. IJTAG simplifies connecting any number of IJTAG-compliant IP blocks into an integrated, hierarchical network, allowing access … Read More
- Esperanto for ICs
- Mentor's TSMC OIP Presentations Now Available!
- Is your car safe to drive? Are you sure?
- Can You Benefit from Cell-Aware Test?
- Are you the 1%?
- Low Power, High Performance Design, Verification, and Test
- Apply Memory BIST to External DRAMs
- Automated Test Creation for Mixed Signal IP Using IJTAG
- Creating Plug-and-Play IP Networks in Large SoCs with IEEE P1687 (IJTAG)
- February, 2014
- January, 2014
- October, 2013
- May, 2013