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Silicon Test and Yield Analysis Blog

22 Jul, 2014

Global Warming

Posted by Shelly Stalnaker

Shelly Stalnaker If you’re designing large die such as a system-on-chip (SoC) with high power demands, you’d better be thinking about how to get the heat out. Poor heat dissipation can lead to a sub-optimal packaging solution from cost, size, weight and performance perspectives. Historically, designers assumed the die temperature was uniform. Not any more. Heating due to current leakage makes power dissipation … Read More

21 Jul, 2014

Won't You Please, Please Help Me?

Posted by Shelly Stalnaker

Shelly Stalnaker No, that’s not really a cry for help, at least not from me. But I can imagine a lot of designers saying just that as they try to understand and implement multi-patterning requirements. LELE? LELELE? LELELELE? SADP? SADP SIT? Whhaaaatttt???!!! And help we have. In spades. Our resident multi-patterning expert, David Abercrombie, not only writes extensively about multi-patterning issues, but he is … Read More

20 Mar, 2014

3D Yoga

Posted by Shelly Stalnaker

Shelly Stalnaker

I practice yoga because it helps with my flexibility. Of course, that’s a little like saying that lighting a candle helps with heating your house, but I digress. The point is, flexibility is generally a good thing, and that holds true for 3D ICs and their test strategies. As discussed in the Electrical Engineering Journal, a flexible 3D test strategy that uses a “plug-and-play” architecture

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Silicon Test, Etienne Racine, IC test, 3DIC, Martin Keim, Ron Press, IEEE P1687, IJTAG

17 Mar, 2014

Little Orphan Annie

Posted by Shelly Stalnaker

Shelly Stalnaker

Is design-for-test the forgotten stepchild of IC design? Not any more, and DFT engineers can, in large part, thank the automotive industry. The number of processors built into a vehicle is steadily increasing, as we all know (okay, maybe not that guy driving the 1969 Chevy Camaro). These chips have to meet very high standards for quality and reliability, which means the companies who make them need

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automotive test, Silicon Test, Cell-Aware ATPG, cell-aware, ATPG, logic BIST, Cell Aware Test, Ron Press, embedded compression, semiconductor test, iso26262

18 Feb, 2014

Esperanto for ICs

Posted by Shelly Stalnaker

Shelly Stalnaker In Standards & Travels on EE Times, Bruce Swanson reminisces about a trip he took to Europe, long before there were cell phones, a common currency, or even the Internet. Dealing with different languages, different currencies, and different local customs took time, was a bit frustrating, and sometimes led to mistakes (WHERE is this train going?!). His experiences on that trip came to mind recently … Read More

IEEE standard, IJTAG, desgin for test, yield analysis, P1687, Silicon Test

13 Feb, 2014

Is your car safe to drive? Are you sure?

Posted by Shelly Stalnaker

Shelly Stalnaker The number of electronic devices used in vehicles is increasing exponentially, for everything from braking to engine control to navigation to collision avoidance. Devices used in safety-critical applications like these not only require very high quality testing at the time of manufacture, but also built-in self-test capability, so they can be tested within the safety-critical application. Advanced design-for-test … Read More

16 Jan, 2014

Can You Benefit from Cell-Aware Test?

Posted by Shelly Stalnaker

Shelly Stalnaker With the move to small geometries, existing fault models such as stuck-at, transition, bridging, open, and small-delay are becoming less effective at ensuring desired quality levels. While these models only consider faults on cell inputs/outputs and interconnect lines between cells, more defects increasingly occur within the cell structures. A new cell-aware test that directly targets specific shorts, … Read More

test pattern, Tessent, defect detection, ATPG, IC, scan test, fault models, FinFET

14 Jan, 2014

Are you the 1%?

Posted by Shelly Stalnaker

Shelly Stalnaker Do you have a product that has been manufactured for quite some time at a high volume? If so, maybe it makes financial sense to chase down that last 1% of yield loss. In Geir Eide’s article on EDN.com, he explains how diagnosis-driven yield analysis (DDYA) can help you quickly and efficiently identify the root cause of yield loss, and separate design-based from process-based yield loss. Still … Read More

yield loss, diagnosis-drive yield analysis, Foundry, DDYA, root cause analysis, root cause deconvolution, layout-aware can diagnosis, RCD

14 Jan, 2014

Shelly Stalnaker If you’re designing low power, high performance ICs, you need to understand the design, verification, and test requirements that these products require. Elements like accurate, efficient hierarchical power grid analysis, leakage optimization, electromigration analysis, and BIST strategies for low-power designs. Learn about all of these, and more, in the Power-Aware A-Z blog at Semiconductor Engineering. … Read More

electromigration, leakage optimization, BIST strategy, power-efficient design, low power design, power grid analysis

29 Oct, 2013

Apply Memory BIST to External DRAMs

Posted by Shelly Stalnaker

Shelly Stalnaker Technical Article 3D-stacked designs containing a mix of separate logic and memory die represent a somewhat new application for memory BIST (built-in self-test), compared to the more conventional single-die embedded SRAM implementations. Gaining access to a DRAM requires predefined customized memory operations that provide a cost-effective solution for testing 3D ICs. EDA tools must make this definition … Read More

31 May, 2013

Gene Forte The creation of test patterns for mixed signal IP has been, to a large extent, a manual effort. The new IEEE P1687 standard, also called IJTAG, simplifies the access, control and testing of embedded IP, and is expected to be rapidly and widely adopted by the semiconductor industry. Mentor Graphics and NXP Semiconductors (NXP) worked together to implement P1687 on mixed-signal IPs in a 65 nm automotive … Read More

IP, P1687, IJTAG

17 May, 2013

admin Integration and testing of IP blocks in large SOCs has been a manual, time consuming design effort. A new standard called IEEE P1687 (or "IJTAG") for IP plug-and-play integration was created to simplify these tasks and EDA tools are emerging to support the standard. IJTAG simplifies connecting any number of IJTAG-compliant IP blocks into an integrated, hierarchical network, allowing access … Read More

IJTAG, IP, IEEE P1687, JTAG, SoC

 
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