With the move to small geometries, existing fault models such as stuck-at, transition, bridging, open, and small-delay are becoming less effective at ensuring desired quality levels. While these models only consider faults on cell inputs/outputs and interconnect lines between cells, more defects increasingly occur within the cell structures. A new cell-aware test that directly targets specific shorts, opens, and transistor defects internal to each standard cell is now available. But you don’t have to be working at the leading-edge nodes to benefit. Silicon results across a large range of technology nodes, from 350nm to FinFETs, have shown significant additional defect detection beyond standard stuck-at and transition patterns when using Cell-Aware ATPG. To learn more, download a copy of our white paper, Tessent Cell-Aware Test, and see how you can improve defect detection in your test processes.
Can You Benefit from Cell-Aware Test?
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