Integration and testing of IP blocks in large SOCs has been a manual, time consuming design effort. A new standard called IEEE P1687 (or "IJTAG") for IP plug-and-play integration was created to simplify these tasks and EDA tools are emerging to support the standard. IJTAG simplifies connecting any number of IJTAG-compliant IP blocks into an integrated, hierarchical network, allowing access to them from a single point. IJTAG saves engineering time and potentially can reduce test time and tester memory requirements. Read more
Creating Plug-and-Play IP Networks in Large SoCs with IEEE P1687 (IJTAG)
More Blog Posts
- 3D Yoga
- Little Orphan Annie
- Esperanto for ICs
- Is your car safe to drive? Are you sure?
- Can You Benefit from Cell-Aware Test?
- Are you the 1%?
- Low Power, High Performance Design, Verification, and Test
- Apply Memory BIST to External DRAMs
- Automated Test Creation for Mixed Signal IP Using IJTAG
- Creating Plug-and-Play IP Networks in Large SoCs with IEEE P1687 (IJTAG)
- March, 2014
- February, 2014
- January, 2014
- October, 2013
- May, 2013